Dual-PFD feedback delay generation circuit

Patent metadata

Field	Value
Publication number	US-10439620-B2
Application number	US-201715715151-A
Country	US
Kind code	B2
Filing date	Sep 25, 2017
Priority date	Sep 23, 2016
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A dual-PFD circuit with delay feedback generated by a dual-modulus prescaler based on mode control from a feedback delay generation circuit. The PFD circuit can be used with a PLL feedback divider to divide a VCO clock signal VCO_clk and generate FB and FB_DLY signals. The PLL feedback divider includes a dual modulus prescaler to selectively divide the VCO_clk by either M or M+1 (such as 4/5) based on a divide mode control input to generate a prescaled divide signal, and a programmed counter/divider (N counter/1/N divider) to selectively divide the prescaled divide signal to generate the FB signal, and a delay generation circuit to selectively delay the FB signal by a pre-defined delay to generate the FB_DLY signal. The prescaler is responsive to the pre-defined delay from the delay generation circuit to change divide modes. The dual PFD circuit response to the FB and FB_DLY signals in relation to a reference signal to generate a phase comparison signal. the dual-PFD circuit can be used with a charge-pump coupled to the dual PFD circuit, and responsive the phase comparison signal to generate a frequency tuning voltage, for input to a VCO for generating the VCO clock signal. The dual PFD circuit, charge pump and VCO can be used in a PLL frequency synthesizer.

First claim

The invention claimed is:

1. A phase locked loop (PLL) circuit, comprising:
the PLL circuit operable to generate a PLL clock signal PLL_clk with a controlled frequency;
feedback divider circuitry including:
dual modulus prescaler circuitry responsive to a divide mode input to selectively divide the PLL_clk signal by at least prescaler divide modes M and M+1 to generate a prescaled divide signal;
divider circuitry to selectively divide the prescaled divide signal to generate a feedback (FB) signal; and
delay circuitry, clocked by the prescaled divide signal, and responsive to the FB signal to initiate a delay period, and after a pre-defined delay period based on the prescaled divide signal:
to generate a delayed feedback (FB_DLY) signal, and
to generate the divide mode input;

phase frequency detection (PFD) circuitry including first and second PFD circuits responsive respectively to the FB and FB_DLY signals to generate respective first and second phase comparison signals corresponding to phase differences between a reference signal, and respectively the FB and FB_DLY signals.

2. The circuit of claim 1 , wherein the prescaler divide modes are 4 and 5.

3. The circuit of claim 1 , further comprising:
charge-pump circuitry responsive the first and second phase comparison signals to generate a PLL frequency control signal to control the frequency of the PLL_clk signal.

4. The circuit of claim 1 , further comprising one of:
a voltage controlled oscillator (VCO); and
an interface to a VCO external to the PLL circuit;
the VCO responsive to the PLL frequency control signal to generate the PLL_clk signal.

5. The circuit of claim 1 , wherein the PLL circuit is used in a PLL frequency synthesizer.

6. The circuit of claim 3 , wherein
the first PFD circuit is responsive to the FB signal to generate PFD up 1 and dn 1 signals;
the second PFD circuit is responsive to the FB_DLY signal to generated PFD up 2 and dn 2 signals; and
the charge pump circuitry coupled to receive the PFD dn 1 and PFD up 2 signals.

7. A frequency synthesizer circuit, comprising:
a phase locked loop (PLL) circuit to generate a PLL clock signal PLL_clk with a controlled frequency;
the PLL circuit including one of:
a frequency controlled oscillator, or
an interface to a frequency controlled oscillator external to the PLL circuit;
the frequency controlled oscillator responsive to a PLL frequency control signal to generate the PLL_clk signal, and
a control loop to generate the PLL frequency control signal;

the control loop including:
frequency divider circuitry, including:
dual modulus prescaler circuitry responsive to a divide mode input to selectively divide the PLL_clk signal by at least prescaler divide modes M and M+1 to generate a prescaled divide signal;
divider circuitry to selectively divide the prescaled divide signal to generate a feedback (FB) signal; and
delay circuitry, clocked by the prescaled divide signal, ands responsive to the FB signal to initiate a delay period, and after a pre-defined delay period based on the prescaled divide signal:
to generate a delayed feedback (FB_DLY) signal, and
to generate the divide mode input;

dual phase frequency detector (PFD) circuitry including first and second PFD circuits responsive respectively to the FB and FB_DLY signals to generate respective first and second phase comparison signals corresponding to phase differences between respectively the FB and FB_DLY signals, and a reference signal.

8. The frequency synthesizer of claim 7 , wherein the prescaler divide modes are 4 and 5.

9. The frequency synthesizer of claim 7 , wherein the frequency controlled oscillator comprises a voltage control oscillator (VCO).

10. The frequency synthesizer of claim 7 , further comprising:
charge-pump circuitry responsive the first and second phase comparison signals to generate a PLL frequency control signal to control the frequency of the PLL_clk signal.

11. The frequency synthesizer of claim 10 , wherein
the first PFD circuit is responsive to the FB signal to generate PFD up 1 and dn 1 signals;
the second PFD circuit is responsive to the FB_DLY signal to generated PFD up 2 and dn 2 signals; and
the charge pump circuitry coupled to receive the PFD dn 1 and PFD up 2 signals.

12. A method for controlling a phase locked loop (PLL), including phase frequency detection (PFD), comprising:
generating a PLL clock signal PLL_clk with a controlled frequency based on a PLL frequency control signal;
dividing the PLL_clk signal by:
selectively dividing the PLL_clk signal with a dual modulus prescaler with at least prescaler divide modes M and M+1 based on a divide mode input, to generate a prescaled divide signal;
selectively dividing the prescaled divide signal to generate a feedback (FB) signal; and
responsive to the FB signal, initiating a pre-defined delay period, and after the delay period based on the prescaled divide signal:
generating a delayed feedback (FB_DLY) signal, and
generating the divide mode input;

based respectively on the FB and FB_DLY signals, generating first and second phase comparison signals corresponding to phase differences between respectively the FB and FB_DLY signals, and a reference signal; and
generating the PLL frequency control signal based on the first and second phase comparison signals.

13. The method of claim 12 , wherein the prescaler divide modes are 4 and 5.

14. The method of claim 12 , wherein the PLL_clk signal is generated by a voltage controlled oscillator (VCO) responsive to the PLL frequency control signal.

15. The method of claim 12 , wherein the PLL frequency control signal is generated by a charge pump responsive the first and second phase comparison signals.

16. The method of claim 15 , wherein
the first phase comparison signal comprises PFD up 1 and dn 1 signals;
the second phase comparison signal comprises PFD up 2 and dn 2 signals; and
the PLL frequency control signal is based on the PFD dn 1 and PFD up 2 signals.

17. The method of claim 12 , wherein the PLL comprises a frequency synthesizer.

Assignees

• Texas Instruments Inc

Inventors

• Srinivas Theertham
• Goyal Jagdish Chand
• Mirajkar Peeyoosh

Classifications

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L2207/10

  Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path · CPC title

• H03L7/1974

  for fractional frequency division · CPC title