Semiconductor device, wafer, and wafer manufacturing method

Patent metadata

Field	Value
Publication number	US-12438111-B2
Application number	US-202217901448-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Mar 23, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX 1 and PX 2 , respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY 1 and PY 2 , respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.

PX1>PY1  (1)

PY2>PX2  (2).

First claim

What is claimed is:

1. A semiconductor device comprising:
a first stacked body; and
a second stacked body bonded to the first stacked body,
wherein the first stacked body includes:
a first wiring; and
a first pad disposed on a first bonding surface, the first stacked body and the second stacked body bonded to the first bonding surface, and electrically connected to the first wiring via a first via,

wherein the second stacked body includes:
a second wiring; and
a second pad electrically connected to the second wiring via a second via, the second pad bonded to the first pad, and

wherein a direction from the first stacked body to the second stacked body is a first direction, a direction intersecting with the first direction is a second direction, and a direction intersecting with the first direction and the second direction is a third direction, and
when a dimension of the first pad in the third direction is PX 1 , the dimension of the first pad in the second direction is PY 1 , a dimension of the second pad in the third direction is PX 2 , and the dimension of the second pad in the second direction is PY 2 , the dimension of the first pad and the dimension of the second pad satisfy at least one of Equations (1) or (2) below,
PX1>PY1  (1), or

PY2>PX2  (2).

2. The semiconductor device according to claim 1 , wherein at least one of the first pad or the second pad is substantially rectangular in a plan view from the first direction.

3. The semiconductor device according to claim 1 , wherein the dimension of the first pad and the dimension of the second pad satisfy at least one of Equations (3) or (4) below,
PX1>PX2  (3), or

PY2>PY1  (4).

4. The semiconductor device according to claim 1 , wherein the first stacked body further includes:
a substrate;
a logic circuit provided on the substrate; and
a plurality of first dummy pads disposed above the logic circuit, disposed on the first bonding surface, and electrically isolated from the logic circuit, wherein the second stacked body further includes:
a plurality of second dummy pads disposed on the plurality of first dummy pads; and
a memory cell array disposed above the plurality of second dummy pads, and

wherein the plurality of first dummy pads and the plurality of second dummy pads are substantially square in a plan view from the first direction.

5. A wafer comprising:
a third wafer including a plurality of first units, each first unit having a logic circuit;
a fourth wafer bonded to the third wafer, the further wafer including a plurality of second units disposed corresponding to the plurality of first units, each second unit having a memory cell array; and
a plurality of third pads (i) electrically connected to the logic circuit disposed on a first bonding surface of the third wafer and the fourth wafer, and (ii) disposed in each of the plurality of first units, the memory cell array disposed in each of the plurality of second units,
wherein each of the plurality of first units further includes:
a third wiring disposed between the logic circuit and any one of the plurality of third pads in a first direction from the third wafer to the fourth wafer, the third wiring electrically connecting the logic circuit to any one of the plurality of third pads; and
a third via disposed on the third wiring, the third via electrically connecting the third wiring to any one of the plurality of third pads, and

wherein a third unit and a fourth unit among the plurality of first units are arranged in a second direction intersecting with the first direction, and
a relative position of the third via on the third wiring in the second direction is different in the third unit and the fourth unit.

6. A wafer comprising:
a third wafer including a plurality of first units, each first unit having a logic circuit;
a fourth wafer including a plurality of second units provided corresponding to the plurality of first units and each second unit having a memory cell array, and bonded to the third wafer; and
a plurality of fourth pads (i) electrically connected to the memory cell array provided on a first bonding surface of the third wafer and the fourth wafer, and (ii) disposed in each of the plurality of second units, the logic circuit disposed in each of the plurality of first units,
wherein each of the plurality of second units includes:
a fourth wiring disposed between the memory cell array and any one of the plurality of fourth pads in a first direction from the third wafer to the fourth wafer, the fourth wiring electrically connecting the memory cell array to any one of the plurality of fourth pads; and
a fourth via disposed on the fourth wiring and electrically connecting the fourth wiring to any one of the plurality of fourth pads, and

wherein a fifth unit and a sixth unit of the plurality of second units are arranged in a second direction intersecting with the first direction, and
a relative position of the fourth via on the fourth wiring in the second direction is different in the fifth unit and the sixth unit.

Assignees

• Kioxia Corp

Inventors

• Iwashita Yasunori
• Arai Shinya
• Nakatsuka Keisuke
• Ashidate Hiroaki

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/967

  Multiple bond pads having different functions · CPC title

• H10W72/963

  Providing mechanical bonding or support, e.g. dummy bond pads · CPC title