Reconfigurable PUF with two PUF functions

Patent metadata

Field	Value
Publication number	US-12437119-B2
Application number	US-202418420636-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Oct 27, 2023
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A reconfigurable PUF with two PUF functions comprises 2 m ×n PUF cells, a sequential control module, a row selection module, n amplification modules, n first bit lines, and n second bit lines. Each of the 2 m ×n PUF cells comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor. The PUF cells can provide two independent responses, and can operate in a SRAM mode and an inverter mode. Therefore, the reconfigurable PUF with two PUF functions can operate both in the SRAM mode and the inverter mode, and a PUF operating mode with higher reliability is selected for generating final responses.

First claim

What is claimed is:

1. A reconfigurable physically unclonable function (PUF) with two PUF functions, comprising 2 m ×n PUF cells, a sequential control circuit, a row selection circuit, n amplification circuits, n first bit lines, and n second bit lines, wherein m is an integer greater than or equal to 1, n is an integer greater than or equal to 1,
wherein the row selection circuit has an enable terminal, m output terminals, 2 m first output terminals and 2 m second output terminals, m bits of row selection signals are input to the m input terminals of the row selection circuit, the row selection circuit is configured to convert the m bits of row selection signals into 2 m bits of row address signals and 2 m bits of row initialization signals, configured to output the 2 m bits of row address signals via the 2 m first output terminals of the row selection circuit, and configured to output the 2 m bits of row initialization signals via the 2 m second output terminals of the row selection circuit, the 2 m bits of row address signals and the 2 m bits of row initialization signals are all binary data, only one bit of data in the 2 m bits of row address signals is 1, the other bits of data of the 2 m bits of row address signals are all 0, only one bit of data of the 2 m bits of row initialization signals is 0, the other bits of data of the 2 m bits of row initialization signals are all 1, the k th bit of data of the 2 m bits of row address signals is output via the k th first output terminal of the row selection circuit, the k th bit of data of the 2 m bits of row initialization signals is output via the k th second output terminal of the row selection circuit, the k th bit of data of the 2 m bits of row address signals is different from the k th bit of data of the 2 m bits of row initialization signals, and k=1, 2, . . . , 2 m ;
wherein each of the n amplification circuits has an enable terminal, a first input terminal, a second input terminal and an output terminal;
wherein the sequential control circuit has a first control terminal and a second control terminal, and is configured to generate two paths of enable signals for controlling sequential matching of the row selection circuit and the n amplification circuits, wherein a first path of an enable signal is output via the first control terminal of the sequential control circuit, and a second path of an enable signal is output via the second control terminal of the sequential control circuit;
wherein the 2 m ×n PUF cells are distributed in 2 m rows and n columns to form a PUF array; each PUF cell has a power terminal, a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal; the first control terminal of the sequential control circuit is connected to the enable terminal of the row selection module, the second control terminal of the sequential control circuit is connected to the enable terminals of the n amplification circuits, the k th first output terminal of the row selection circuit is connected to the first input terminals of the n PUF cells in the k th row of the PUF array, the k th second output terminal of the row selection circuit is connected to the second input terminals of the n PUF cells in the k th row of the PUF array, the first output terminals of the 2 m PUF cells in the j th column of the PUF array are all connected to the j th first bit line, the j th first bit line is connected to the first input terminal of the j th amplification circuit, the second output terminals of the 2 m PUF cells in the j th column of the PUF array are all connected to the j th second bit line, the j th second bit line is connected to the second input terminal of the j th amplification circuit, and j=1, 2, . . . , n;
wherein when data input to the first input terminals of the n PUF cells in one row of the PUF array is 1 and data input to the second input terminals of the n PUF cells in said row of the PUF array is 0, the n PUF cells enter an operating state, the first output terminal and the second output terminal of each PUF cell in said row respectively generate and output voltage signals, all the PUF cells in the other rows enter a dormant state, and the first output terminals and the second output terminals of the PUF cells in the other rows do not output voltage signals; each PUF cell comprises a first P-channel metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel Metal Oxide Semiconductor (NMOS) transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a seventh NMOS transistor, wherein a source of the first PMOS transistor and a source of the second PMOS transistor are connected and a connecting terminal thereof is the power terminal of the PUF cell, a gate of the first PMOS transistor, a drain of the second PMOS transistor, a drain of the sixth NMOS transistor, a source of the fourth NMOS transistor, a gate of the second NMOS transistor, a drain of the first NMOS transistor and a drain of the third NMOS transistor are connected, a drain of the first PMOS transistor, a gate of the second PMOS transistor, a source of the fifth NMOS transistor, a drain of the second NMOS transistor, a drain of the seventh NMOS transistor, a drain of the fourth NMOS transistor and a gate of the third NMOS transistor are connected, a gate of the first NMOS transistor and a gate of the seventh NMOS transistor are connected and a connecting terminal thereof is the second input terminal of the PUF cell, a source of the first NMOS transistor, a source of the third NMOS transistor, a source of the second NMOS transistor and a source of the seventh NMOS transistor are all grounded, a gate of the fourth NMOS transistor is the third input terminal of the PUF cell, a gate of the fifth NMOS transistor and a gate of the sixth NMOS transistor are connected and a connecting terminal thereof is the first input terminal of the PUF cell, a drain of the fifth NMOS transistor is the first output terminal of the PUF cell, and a source of the sixth NMOS transistor is the second output terminal of the PUF cell;
wherein the reconfigurable PUF with two PUF functions further comprises a bit configuration circuit and a biasing circuit, wherein the bit configuration circuit has n output terminals, the j th output terminal of the bit configuration circuit is connected to the third input terminals of the 2 m PUF cells in the j th column of the PUF cell, the bit configuration circuit is configured to generate n bits of binary configuration signals, and the j th bit of the n bits of binary configuration signals is output via the j th output terminal of the bit configuration circuit;
wherein when the j th bit of the n bits of binary configuration signals is 1, the 2 m PUF cells in the j th column of the PUF cell are configured to be in an inverter mode;
wherein when the j th bit of the n bits of binary configuration signals is 0, the 2 m PUF cells in the j th column of the PUF cells are configured to be in a SRAM mode;
wherein the biasing circuit has n output terminals, the j th output terminal of the biasing circuit is connected to the power terminals of the 2 m PUF cells in the j th column of the PUF cell, the biasing circuit is configured to generate n paths of bias voltages, wherein the n th path of bias voltage is output via the j th output terminal of the biasing circuit;
wherein when one PUF cell enters the operating state and is in the SRAM mode, a large voltage deviation is generated due to the cross-coupled inverters competition between the first bit line and the second bit line which are connected to the first output terminal and the second output terminal of said PUF cell, wherein the first bit line theoretically generates a voltage equal to a bias voltage input to th

Assignees

• Univ Wenzhou

Inventors

• Wang Pengjun
• Ni Li
• Li Gang
• Ye Hao
• Jin Cai Long

Classifications

• H03K19/17764

  for reliability · CPC title

• H03K19/17704

  the logic functions being realised by the interconnection of rows and columns · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• Y02D30/70

  in wireless communication networks · CPC title