Systems and methods utilizing DAX memory management for testing CXL protocol enabled devices

Patent metadata

Field	Value
Publication number	US-12436855-B2
Application number	US-202318129422-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	Sep 21, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester includes a direct access device (DAX) interface that prevents corruption of DUTs. In one exemplary implementation, the tester isolates testing of a particular CXL enabled DUT from undesirable interference and corruption. The tester can prevent inappropriate writing over the DUT's memory. The DUTs reside in the separate per-device space of a Linux operating system rather than an extension of memory space. One of the plurality of DUTs can be a CXL type 3 memory expander device. In one exemplary implementation, the direct access device (DAX) interface creates a unique DAX instance for each individual DUT included in the plurality of DUTs

First claim

The invention claimed is:

1. A test system comprising:
a user interface configured to enable user interaction with the system;
a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and
a tester configured to perform direct testing of the plurality of DUTs, wherein the tester comprises a direct access device (DAX) component that prevents corruption of DUTs, wherein the direct access device (DAX) component creates a unique DAX instance for each individual DUT included in the plurality of DUTs.

2. The test system of claim 1 , wherein the tester isolates testing of a particular CXL enabled DUT from undesirable interference and corruption.

3. The test system of claim 1 , wherein the tester prevents inappropriate writing over a DUT's memory.

4. The test system of claim 1 , wherein the DUTs reside in a separate per-device memory space of a Linux operating system rather than extension of memory space.

5. The test system of claim 1 , wherein one of the plurality of DUTs is a CXL type 3 memory expander device.

6. A device testing management method comprising:
performing a persistent device representation process for a compute express link (CXL) protocol compliant device under test (DUT), wherein the persistent device representation process comprises naming the DUT with a name, wherein the name is created automatically on top of a LINUX enumeration and wherein further the DUT resides in a separate per device space of a direct access device (DAX) memory interface:
performing a device power up cleanup process; and
performing a device power down cleanup process.

7. The device testing management test method of claim 6 , wherein the performing a persistent device representation process comprises assigning and tracking the CXL compliant DUT, including characteristics of the CXL compliant DUT, based upon a reference indicator that is unique to the CXL compliant DUT, wherein the reference indicator is persistent while the CXL compliant DUT is communicatively coupled to a test board.

8. The device testing management method of claim 7 , wherein the reference indicator is based upon a test board location slot utilized to communicatively couple the CXL compliant DUT.

9. The device testing management method of claim 6 , wherein a test board location based name ensures a tester is able to target the CXL compliant DUT and is persistent while the CXL compliant DUT is communicatively coupled to the-a load board.

10. The device testing management method of claim 6 , wherein the device power down clean up process comprises a flushing process for a central processing unit (CPU) and cache included in a host in a tester.

11. The device testing management method of claim 10 , where the flushing process comprises flushing data in addresses that were written to in operations associated with testing of the CXL compliant DUT, wherein the addresses are included in a range mapped to the CXL compliant DUT.

12. The device testing management method of claim 6 , wherein the device power up cleanup process comprises waiting for a BIOS enumeration process without scanning device.

13. A test system comprising:
a user interface configured to enable user interaction with the system;
a test board configured to communicatively couple with a compute express link (CXL) protocol compliant device under test (DUT); and
a tester configured to perform direct testing of the CXL compliant DUT, wherein the tester assigns and tracks the CXL compliant DUT, including characteristics of the CXL compliant DUT, based upon a reference indicator that is unique to the CXL compliant DUT, and wherein further the reference indicator is persistent while the CXL compliant DUT is communicatively coupled to the test board.

14. The test system of claim 13 , wherein the reference indicator is based upon a test board location.

15. The test system of claim 14 , wherein the test board location is a slot included in the test board and wherein the CXL compliant DUT is communicatively coupled to the test board via the slot.

16. The test system of claim 13 , wherein the tester assigns and tracks the CXL compliant DUT via a reference indicator in a device space.

17. The test system of claim 13 , wherein the reference indicator is a DAX device representation.

18. The test system of claim 13 , wherein the tester isolates testing of a particular CXL compliant DUT from undesirable interference and corruption.

Assignees

• Advantest Corp

Inventors

• Malisic Srdjan
• Yuan Chi

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/53 Primary

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title

• G06F11/27

  Built-in tests · CPC title

• G06F11/2205

  using arrangements specific to the hardware being tested · CPC title