Providing fine grain access to package memory

Patent metadata

Field	Value
Publication number	US-12436711-B2
Application number	US-202217708398-A
Country	US
Kind code	B2
Filing date	Mar 30, 2022
Priority date	Mar 30, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a first die having a plurality of cores, each of the plurality of cores comprising:
a scheduler to schedule tasks for execution on an execution circuit;
the execution circuit to execute the tasks;
and a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM);

a second die comprising the DRAM, the DRAM comprising a plurality of local portions, wherein at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die; wherein each of the plurality of cores further comprises an interface circuit to couple the core to a first nearest neighbor core and a second nearest neighbor core, wherein the interface circuit is to store a first processed data in the corresponding local portion of the DRAM, and to send the first processed data to the local memory portion of the first nearest neighbor core, wherein the first nearest neighbor core is to further process the first processed data.

2. The apparatus of claim 1 , wherein the at least some of the plurality of cores comprises a translation lookaside buffer (TLB) to map virtual addresses to physical addresses only for the local portion of the DRAM.

3. The apparatus of claim 2 , wherein the TLB is to use a portion of address bits of an address space for the DRAM to map the virtual addresses to the physical addresses only for the local portion of the DRAM.

4. The apparatus of claim 1 , wherein the local memory interface circuit is to access only the local portion of the DRAM.

5. The apparatus of claim 1 , wherein each of the plurality of local portions of the DRAM has a width of at least 1024 words.

6. The apparatus of claim 1 , wherein the apparatus comprises an integrated circuit package having the first die and the second die, wherein the DRAM is to be a system memory for a system in which the integrated circuit package is included.

7. The apparatus of claim 6 , wherein each of the plurality of cores further comprises a local cache, and wherein the integrated circuit package comprises a flat memory hierarchy, the flat memory hierarchy having only the local cache and the DRAM.

8. The apparatus of claim 1 , wherein the second die comprises: a first layer having a first plurality of memory cells for each of the plurality of portions of the DRAM; and a second layer having a second plurality of memory cells for each of the plurality of portions of the DRAM.

9. The apparatus of claim 1 , wherein the at least some of the plurality of cores are directly coupled to the corresponding local portion of the DRAM by a plurality of through silicon vias (TSVs).

10. A package comprising:
a first die having a plurality of cores, each of the plurality of cores comprising a local memory interface circuit to directly access a local portion of a dynamic random access memory (DRAM), the local memory interface circuit comprising a first plurality of through silicon vias (TSVs);
and a second die comprising the DRAM, the DRAM comprising a plurality of local portions, each of the plurality of local portions comprising a second plurality of TSVs, wherein at least some of the plurality of cores are directly coupled to the corresponding local portion of the DRAM by interconnection of the first plurality of TSVs and the second plurality of TSVs;
wherein each of the plurality of cores further comprises an interface circuit to couple the core to a first nearest neighbor core and a second nearest neighbor core, wherein the interface circuit is to store a first processed data in the corresponding local portion of the DRAM, and to send the first processed data to the local memory portion of the first nearest neighbor core, wherein the first nearest neighbor core is to further process the first processed data.

11. The package of claim 10 , wherein the at least some of the plurality of cores comprises a translation lookaside buffer (TLB) to map virtual addresses to physical addresses only for the local portion of the DRAM with a portion of address bits of an address space for the DRAM.

12. The package of claim 10 , further comprising a third die comprising a second DRAM, the second DRAM comprising a plurality of second local portions, each of the plurality of second local portions comprising a third plurality of TSVs, wherein at least some of the plurality of cores are directly coupled to the corresponding second local portion of the second DRAM by interconnection of the first plurality of TSVs and the third plurality of TSVs.

13. The package of claim 12 , wherein the second die comprises a cache memory and the third die comprises a system memory, when the package is implemented in a system lacking an external system memory.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek Anil
• Gomes Wilfred
• Koduri Rajabali
• Ranade Pushkar

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/1024

  Latency reduction · CPC title