Dynamic repartition of memory physical address mapping

Patent metadata

Field	Value
Publication number	US-12436684-B2
Application number	US-202318208639-A
Country	US
Kind code	B2
Filing date	Jun 12, 2023
Priority date	Sep 28, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

First claim

What is claimed is:

1. A method comprising:
relocating first data out of a first set of memory blocks of a first memory device to a second memory device;
repartitioning, without rebooting the first memory device, at least one physical memory map associated with the first memory device to produce at least one repartitioned physical memory map; and
storing the first data at a second set of memory blocks of the first memory device based on the at least one repartitioned physical memory map.

2. The method of claim 1 , further comprising:
preventing repartitioning of a third set of memory blocks in response to an indication that the third set of memory blocks store critical data.

3. The method of claim 2 , wherein the critical data comprises operating system (OS) data, page table data, or both.

4. The method of claim 1 , wherein repartitioning the at least one physical memory map is performed in conjunction with a change in a system configuration of a processing system.

5. The method of claim 1 , wherein repartitioning the at least one physical memory map comprises:
changing a mapping defined by the at least one physical memory map for a first physical address, wherein the at least one physical memory map maps the first physical address to a first memory block of the first set of memory blocks, and the at least one repartitioned physical memory map maps the first physical address to a second memory block of the second set of memory blocks.

6. A processing system comprising:
a plurality of memory devices including a first memory device having a first set of memory blocks; and
at least one processor configured to execute instructions that manipulate the at least one processor to, without rebooting the first memory device:
relocate first data out of the first set of memory blocks of the first memory device;
repartition at least one physical memory map associated with the first memory device to produce at least one repartitioned physical memory map; and
store the first data at a second set of memory blocks of the first memory device based on the at least one repartitioned physical memory map.

7. The processing system of claim 6 , wherein the instructions manipulate the at least one processor to:
disable repartitioning of a third set of memory blocks in response to an indication that the third set of memory blocks store critical data.

8. The processing system of claim 6 , wherein the instructions manipulate the at least one processor to:
repartition the at least one physical memory map in conjunction with a change in a system configuration of the processing system.

9. The processing system of claim 8 , wherein the change in the system configuration corresponds to a change in an error correcting code (ECC) configuration of the processing system, wherein the ECC configuration identifies ECC memory blocks of the plurality of memory devices that are reserved for storing ECC data.

10. The processing system of claim 8 , wherein the change in the system configuration corresponds to a change in an interleaving configuration of the processing system, wherein the interleaving configuration defines at least one interleaving pattern according to which data is to be stored on memory blocks of the plurality of memory devices, the memory blocks including at least the first set of memory blocks.

11. The processing system of claim 10 , wherein the change in the interleaving configuration corresponds to replacing a first interleaving pattern with a second interleaving pattern, and the at least one repartitioned physical memory map reflects the second interleaving pattern.

12. The processing system of claim 6 , wherein to repartition the at least one physical memory map, the instructions manipulate the at least one processor to:
change a mapping defined by the at least one physical memory map for a first physical address, wherein the at least one physical memory map maps the first physical address to a first memory block of the first set of memory blocks and the at least one repartitioned physical memory map maps the first physical address to a second memory block of the second set of memory blocks.

13. A system comprising:
a first memory device having a first memory block at which first data is stored; and
at least one processor configured to execute instructions that manipulate the at least one processor to, without rebooting the first memory device:
transfer first data out of the first memory block;
repartition a physical memory map associated with the first memory block to produce a repartitioned physical memory map; and
store the first data at a second memory block of the first memory device based on the repartitioned physical memory map.

14. The system of claim 13 , further comprising:
a second memory device, wherein the instructions manipulate the at least one processor to relocate the first data from the first memory block to the second memory device and from the second memory device to the second memory block.

15. The system of claim 13 , wherein the instructions further manipulate the at least one processor to:
repartition the physical memory map in conjunction with a change in a system configuration of the system.

16. The system of claim 15 , wherein the change in the system configuration corresponds to a change in an error correcting code (ECC) configuration of the system, wherein the ECC configuration identifies ECC memory blocks of the first memory device that are reserved for storing ECC data.

17. The system of claim 13 , wherein, to repartition the physical memory map, the instructions manipulate the at least one processor to:
change a mapping defined by the physical memory map for a first physical address, wherein the physical memory map associates the first physical address with the first memory block and the repartitioned physical memory map associates the first physical address with the second memory block.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Greathouse Joseph L
• Smith Alan D
• Duran Francisco L
• Kuehling Felix
• Asaro Anthony

Classifications

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• G06F3/064

  Management of blocks · CPC title