Display substrate, display panel, and display apparatus

Patent metadata

Field	Value
Publication number	US-12436639-B2
Application number	US-202218262900-A
Country	US
Kind code	B2
Filing date	Jul 14, 2022
Priority date	Jul 14, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A display substrate includes a display area, which includes a plurality of sub-areas arranged in a first direction. In at least one sub-area, the display substrate further includes a base substrate, a plurality of sub-pixels arranged in a fourth direction, a data line, and a first touch line extending in the fourth direction. The of sub-pixels include a first sub-pixel and a second sub-pixel, at least one first sub-pixel extends in a second direction, and at least one second sub-pixel extends in a third direction. The first, second, third and fourth directions intersect with one another. The data line is electrically connected to the sub-pixels through a plurality of input transistors. At least one input transistor includes a first electrode electrically connected to the sub-pixel. Orthographic projections of the first touch line and the first electrode on the base substrate do not overlap with each other.

First claim

What is claimed is:

1. A display substrate comprising a display area, wherein the display area comprises a plurality of sub-areas arranged in a first direction, and in at least one of the sub-areas, the display substrate further comprises:
a base substrate;
a plurality of sub-pixels disposed on the base substrate, wherein the plurality of sub-pixels are arranged in a fourth direction and comprise at least one first sub-pixel extending in a second direction and at least one second sub-pixel extending in a third direction;
a data line disposed on the base substrate; and
a first touch line disposed on the base substrate, wherein the first touch line extends in the fourth direction, and wherein the first direction, the second direction, the third direction and the fourth direction intersect with one another,
wherein the data line is electrically connected to the plurality of sub-pixels through a plurality of input transistors, at least one of the input transistors comprises a first electrode electrically connected to a respective one of the sub-pixels, and an orthographic projection of the first touch line on the base substrate does not overlap with an orthographic projection of the first electrode on the base substrate;
wherein the orthographic projection of the first touch line on the base substrate is located on a side of an orthographic projection of the data line on the base substrate close to the orthographic projection of the first electrode on the base substrate; and
wherein the sub-area comprises a plurality of partitions arranged in the fourth direction, and in at least one of the partitions:
wherein the plurality of input transistors comprise a first input transistor and a second input transistor, and the data line comprises a first portion, a second portion, a first connecting portion, and a second connecting portion;
wherein a second end of the first portion is electrically connected to a first end of the second portion through the first connecting portion, and a second end of the second portion is electrically connected to a first end of the first portion in a next partition through the second connecting portion; and
wherein a distance between the second connecting portion and the first touch line is less than a distance between the first connecting portion and the first touch line, the first connecting portion is electrically connected to the first sub-pixel through the first input transistor, and the second connecting portion is electrically connected to the second sub-pixel through the second input transistor.

2. The display substrate according to claim 1 , wherein in an x th partition of the plurality of partitions,
the second connecting portion comprises a first inclined portion, a second inclined portion, and a first straight portion connected between the first inclined portion and the second inclined portion; and
an orthographic projection of any of the first inclined portion and the second inclined portion on the base substrate is located on a side of an orthographic projection of the first straight portion on the base substrate close to the orthographic projection of the first touch line on the base substrate,
wherein x is a positive integer.

3. The display substrate according to claim 2 , wherein the orthographic projection of the first inclined portion on the base substrate, the orthographic projection of the second inclined portion on the base substrate and the orthographic projection of the first straight portion on the base substrate define a first pattern, and an orthographic projection of the first electrode of the second input transistor on the base substrate at least partially overlaps with the first pattern.

4. The display substrate according to claim 2 , wherein in the at least one of the partitions, the display substrate further comprises a first shielding portion disposed on the base substrate; and
an orthographic projection of the first shielding portion on the base substrate covers an orthographic projection of the second connecting portion on the base substrate.

5. The display substrate according to claim 4 , wherein in the at least one of the partitions, the display substrate further comprises a second shielding portion disposed on the base substrate, and the second shielding portion is disposed in a same layer as the first shielding portion and is made of a same material as the first shielding portion; and
an orthographic projection of the second shielding portion on the base substrate covers an orthographic projection of the first connecting portion on the base substrate, and a size of the second shielding portion in the fourth direction is less than or equal to a size of the first shielding portion in the fourth direction.

6. The display substrate according to claim 2 , wherein the first connecting portion comprises a second straight portion, and a distance between the second straight portion and the first touch line is greater than a distance between the first straight portion and the first touch line.

7. The display substrate according to claim 1 , wherein in a y th partition of the plurality of partitions,
the orthographic projection of the first touch line on the base substrate is between an orthographic projection of the first electrode of the second input transistor on the base substrate and an orthographic projection of the data line connected to the second input transistor on the base substrate,
wherein y is a positive integer.

8. The display substrate according to claim 7 , wherein in the y th partition of the plurality of partitions,
the orthographic projection of the first touch line on the base substrate partially overlaps with an orthographic projection of an active portion of the second input transistor on the base substrate.

9. The display substrate according to claim 8 , wherein in the y th partition of the plurality of partitions,
the active portion of the second input transistor comprises a first electrode connecting portion, a second electrode connecting portion, a first channel portion, a second channel portion, and a channel connecting portion, wherein the first channel portion and the second channel portion are between the first electrode connecting portion and the second electrode connecting portion, and the channel connecting portion is between the first channel portion and the second channel portion; and
the orthographic projection of the first touch line on the base substrate partially overlaps with an orthographic projection of the channel connecting portion of the second input transistor on the base substrate.

10. The display substrate according to claim 9 , wherein in the y th partition of the plurality of partitions, the display substrate further comprises a third shielding portion; and
an orthographic projection of the third shielding portion on the base substrate covers an orthographic projection of the first channel portion of the second input transistor on the base substrate and an orthographic projection of the second channel portion of the second input transistor on the base substrate.

11. The display substrate according to claim 10 , wherein the third shielding portion is between the input transistor and the base substrate.

12. The display substrate according to claim 10 , wherein in the y th partition of the plurality of partitions, the orthographic projection of the third shielding portion on the base substrate is separated by the orthographic projection of the first touch line on the base substrate.

13. The display substrate according to claim 1 , wherein the orthographic projection of the first touch line on the base substrate is located on a side of an

Assignees

• Boe Technology Group Co Ltd

Inventors

• Qin Wenwen
• Wang Zhen
• Sun Jian
• Xie Jianyun
• Zhang Han
• Wang Deshuai
• Shan Yue
• Zhang Jian
• Yang Xiaoyan
• Yan Wei
• Zhang Yadong

Classifications

• G06F2203/04111

  Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title