Chip with pads of differing width and display module with the same

Patent metadata

Field	Value
Publication number	US-12433128-B2
Application number	US-202117505482-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Mar 19, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

The disclosure provides a chip and a display module with the same. The chip comprises a body, wherein the body is provided with a plurality of junctions which are arranged at intervals in a first direction, at least one junction comprises a first sub-junction and a second sub junction which are arranged in a second direction and formed into an integrated structure, a width of the first sub-junction is greater than a width of the second sub-junction in the first direction, and the second direction is perpendicular to the first direction.

First claim

The invention claimed is:

1. A chip, comprising:
a body, wherein the body is provided with a plurality of junctions which are arranged at intervals in a first direction, at least one said junction comprises a first sub-junction and a second sub-junction which are arranged in a second direction and formed into an integrated structure, a width of the first sub-junction is greater than a width of the second sub-junction in the first direction, the second direction is perpendicular to the first direction,
wherein at least two adjacent said junctions comprise the first sub-junction and the second sub-junction, and
wherein two adjacent instances of the plurality of junctions comprise the first sub-junction and the second sub-junction, and in the first direction, the first sub-junction of one of the junctions is opposite to the second sub-junction of the adjacent junction, and the second sub-junction of one of the junctions is opposite to the first sub-junction of the adjacent junction.

2. The chip according to claim 1 , wherein in the first direction, the first sub junction and the second sub-junction of the junction are arranged coaxially.

3. The chip according to claim 1 , wherein in the first direction, the first sub junction and the second sub-junction of the junction are arranged non-coaxially.

4. The chip according to claim 3 , wherein in the first direction, one end of the first sub-junction of the junction is flush with one end of the second sub-junction.

5. The chip according to claim 1 , wherein any two adjacent said junctions are of a same structure or different structures.

6. The chip according to claim 1 , wherein in the second direction, two ends of plurality of junctions are arranged in a flush manner.

7. The chip according to claim 1 , wherein in the second direction, a length of the first sub-junction is less than or equal to a length of the corresponding second sub-junction.

8. A chip, comprising:
a body, wherein the body is provided with a plurality of junctions which are arranged at intervals in a first direction, at least one said junction comprises a first sub-junction and a second sub-junction which are arranged in a second direction and formed into an integrated structure, a width of the first sub-junction is greater than a width of the second sub-junction in the first direction, the second direction is perpendicular to the first direction,
wherein each of the junctions comprises the first sub-junction and the second sub-junction, the first sub-junction is configured for wire bonding connection with a hard circuit board, and the width of the first sub-junction is greater than a wire bonding width in the first direction.

9. The chip according to claim 1 , wherein at least one of the first sub-junction and the second sub-junction has a rectangle structure.

10. A display module having an active area, comprising:
a chip including a body, wherein the body is provided with a plurality of junctions which are arranged at intervals in a first direction, at least one said junction comprises a first sub-junction and a second sub-junction which are arranged in a second direction and formed into an integrated structure, a width of the first sub-junction is greater than a width of the second sub-junction in the first direction, the second direction is perpendicular to the first direction,
wherein the chip has a first area and a second area spaced apart from each other, the first area is arranged corresponding to the active area, the junctions are arranged in the second area, and the junctions are configured to be formed as signal interfaces.

11. The display module according to claim 10 , further comprising:
a silicon substrate and a cover plate which are oppositely arranged in a third direction;
an organic light-emitting device arranged between the silicon substrate and the cover plate and comprising a pixel driving circuit layer, an anode layer, an organic light-emitting layer and a cathode layer, the pixel driving circuit layer, the anode layer, the organic light-emitting layer and the cathode layer being sequentially stacked in the third direction, and the pixel driving circuit layer being arranged on a side surface, facing the cover plate, of the silicon substrate; and
a color film layer arranged between the cover plate and the organic light-emitting device, packaging layers being arranged between the color film layer and the cover plate and between the color film layer and the organic light-emitting device.

12. The chip according to claim 1 , wherein, in the second direction, a length of the first sub-junction is greater than a length of the corresponding second sub-junction.

13. The chip according to claim 1 , wherein a distance between the two adjacent junctions in the first direction is 110 m, a width of the first sub-junction in the first direction is 70 μm, and a width of the second sub-junction in the first direction is 50 μm.

14. The chip according to claim 12 , wherein the length of the first sub-junction in the second direction is 400 μm, and the length of the second sub-junction in the second direction is 300 μm.

15. The chip according to claim 1 , wherein in the second direction, a length of the first sub-junction is less than a length of the corresponding second sub-junction, the length of the first sub-junction in the second direction is 300 μm, and the length of the second sub-junction in the second direction is 400 μm.

16. The chip according to claim 1 , wherein mark areas are reserved on both sides of the body in the first direction, a width of the mark areas is 500 μm, and a distance between one end of the junctions and an edge of the body is 110 μm.

17. The chip according to claim 1 , wherein a portion of the plurality of junctions protrude out of the body and other portion of the plurality of junctions are recessed into the body to help an operator to identify positions of the plurality of junctions.

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Junbo
• Yang Shengji
• Lu Pengcheng
• Zhu Zhijian
• Huang Kuanta
• Tian Yuanlan

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/547

  Dispositions of multiple bond wires · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title