Display substrate, preparation method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-12433109-B2
Application number	US-202117637456-A
Country	US
Kind code	B2
Filing date	Apr 28, 2021
Priority date	Apr 28, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

Provided are a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a first semi-conductive layer, a first conductive layer, a second conductive layer, a second semi-conductive layer, a third conductive layer, an interlayer insulating layer and an organic layer stacked on a substrate. The first semi-conductive layer includes an active layer of a polysilicon transistor, the first conductive layer includes a gate electrode of a polysilicon transistor and a first electrode plate of a storage capacitor, the second conductive layer includes a second electrode plate of a storage capacitor, the second semi-conductive layer includes an active layer of an oxide transistor, and the third conductive layer includes a gate electrode of an oxide transistor.

First claim

The invention claimed is:

1. A display substrate, wherein
in a direction perpendicular to the display substrate, the display substrate comprises:
a substrate, and
a first semi-conductive layer, a first conductive layer, a second conductive layer, a second semi-conductive layer, a third conductive layer, an interlayer insulating layer and an organic layer stacked on the substrate,
wherein the first semi-conductive layer comprises an active layer of at least one polysilicon transistor, the first conductive layer comprises a gate electrode of at least one polysilicon transistor and a first electrode plate of a storage capacitor, the second conductive layer comprises a second electrode plate of a storage capacitor, the second semi-conductive layer comprises an active layer of at least one oxide transistor, and the third conductive layer comprises a gate electrode of at least one oxide transistor;
wherein the interlayer insulating layer is provided with a plurality of vias and a plurality of grooves, there is at least an overlapping region between an orthographic projection of the plurality of vias on the substrate and an orthographic projection of at least one of the first semi-conductive layer, the first conductive layer, the second conductive layer, the second semi-conductive layer and the third conductive layer on the substrate, and the plurality of grooves are filled with the organic layer;
wherein the polysilicon transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, and the oxide transistor comprises an eighth transistor;
wherein the display substrate comprises a plurality of sub-pixels, wherein the sub-pixels comprise a first region, a second region and a third region, and the second region is disposed between the first region and the third region;
wherein the plurality of grooves comprises a fourth groove; and
wherein the fourth groove is disposed in the second region, and there is at least an overlapping region between an orthographic projection of the fourth groove on the substrate and an orthographic projection of an active layer of the fourth transistor on the substrate; and there is at least an overlapping region between the orthographic projection of the fourth groove on the substrate and an orthographic projection of the second electrode plate on the substrate.

2. The display substrate of claim 1 , wherein there is at least a non-overlapping region between an orthographic projection of the plurality of grooves on the substrate and an orthographic projection of the gate electrode of the oxide transistor on the substrate.

3. The display substrate of claim 1 , wherein the plurality of grooves comprises a second groove;
there is at least a non-overlapping region between an orthographic projection of the second groove on the substrate and an orthographic projection of the first semi-conductive layer on the substrate; and there is at least a non-overlapping region between the orthographic projection of the second groove on the substrate and an orthographic projection of the second semi-conductive layer on the substrate.

4. The display substrate of claim 1 , wherein:
the first transistor, the second transistor, the fourth transistor and the eighth transistor are disposed in the first region;
the third transistor and the storage capacitor are disposed in the second region; and
the fifth transistor, the sixth transistor and the seventh transistor are disposed in the third region.

5. The display substrate of claim 4 , wherein the plurality of vias comprise a first via, a second via, a third via, a fourth via, a fifth via, a sixth via, a seventh via and an eighth via;
a second electrode plate of the storage capacitor comprises an opening, and an orthographic projection of the first via on the substrate is within a range of an orthographic projection of the opening on the substrate, and there is at least an overlapping region between the orthographic projection of the first via on the substrate and an orthographic projection of the first electrode plate on the substrate;
an orthographic projection of the second via on the substrate is within a range of an orthographic projection of the second electrode plate on the substrate, and there is at least an overlapping region between the orthographic projection of the second via on the substrate and the orthographic projection of the second electrode plate on the substrate;
there is at least an overlapping region between an orthographic projection of the third via on the substrate and an orthographic projection of a first electrode of the fifth transistor on the substrate;
there is at least an overlapping region between an orthographic projection of the fourth via on the substrate and an orthographic projection of an second electrode of the sixth transistor on the substrate;
there is at least an overlapping region between an orthographic projection of the fifth via on the substrate and an orthographic projection of a first electrode of the fourth transistor on the substrate;
there is at least an overlapping region between an orthographic projection of the sixth via on the substrate and an orthographic projection of a first electrode of the second transistor on the substrate;
there is at least an overlapping region between an orthographic projection of the seventh via on the substrate and an orthographic projection of a first electrode of the seventh transistor on the substrate; and
there is at least an overlapping region between an orthographic projection of the eighth via on the substrate and an orthographic projection of a first electrode of the first transistor on the substrate.

6. The display substrate of claim 4 , wherein the first conductive layer comprises a first scanning signal line, a second scanning signal line, an light emitting control line and the first electrode plate of the storage capacitor, and the second conductive layer comprises a first shielding layer, the second electrode plate of the storage capacitor and an electrode plate connecting line; the third conductive layer comprises a third scanning signal line and a second initial signal line;
the first scanning signal line, the third scanning signal line and the second initial signal line extend along a first direction and are disposed in the first region;
the first electrode plate, the second electrode plate and the electrode plate connecting line of the storage capacitor are all disposed in the second region; and
the second scanning signal line, the light emitting control line and the first shielding layer all extend along the first direction and are disposed in the third region.

7. The display substrate of claim 6 , wherein the plurality of vias comprise a ninth via, a tenth via and an eleventh via;
there is at least an overlapping region between an orthographic projection of the ninth via on the substrate and an orthographic projection of the second initial signal line on the substrate;
there is at least an overlapping region between an orthographic projection of the tenth via on the substrate and an orthographic projection of a first electrode of the eighth transistor on the substrate; and
there is at least an overlapping region between an orthographic projection of the eleventh via on the substrate and an orthographic projection of a second electrode of the eighth transistor on the substrate.

8. The display substrate of claim 6 , wherein the plurality of grooves comprises a third groove;
the third groove is disposed in the second region, and there is at least an overlapping region between an orthographic projection of the third groove on the substrate and an orthographic projection of an active layer o

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Ding Xiaoqi
• Huang Peng
• Liu Ke
• Gao Tao
• Yang Xinlei
• Cui Guoyi
• Li Zeliang
• Lu Hui

Classifications

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title