Compound semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-12432995-B2
Application number	US-202217835956-A
Country	US
Kind code	B2
Filing date	Jun 8, 2022
Priority date	May 16, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. A bi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film.

First claim

What is claimed is:

1. A compound semiconductor device, comprising:
a substrate;
a buffer layer on the substrate;
a channel layer on the buffer layer, wherein the buffer layer has a band gap larger than a band gap of the channel layer;
a barrier layer on the channel layer;
a passivation layer on the barrier layer;
a contact area recessed into the passivation layer and the barrier layer, wherein the channel layer is partially exposed at a bottom of the contact area;
a bi-layer silicide film on the contact area, wherein the bi-layer silicide film comprises a first silicide layer in direct contact with the channel layer and a second silicide layer in direct contact with the first silicide layer, wherein the second silicide layer comprises a recessed region formed by inclined sidewalls and a bottom surface; and
a copper contact on the bi-layer silicide film, wherein the copper contact comprises a diffusion barrier layer in direct contact with the second silicide layer, and a copper metal layer in direct contact with the diffusion barrier layer, wherein the copper contact is formed only within the recessed region.

2. The compound semiconductor device according to claim 1 , wherein the first silicide layer has a work function smaller than that of the second silicide layer, and the second silicide layer has a work function smaller than that of the diffusion barrier layer of the copper contact.

3. The compound semiconductor device according to claim 1 , wherein the first silicide layer has a thickness smaller than that of the second silicide layer, and wherein the first silicide layer is in direct contact with a sidewall of the barrier layer.

4. The compound semiconductor device according to claim 3 , wherein the first silicide layer has a thickness smaller than or equal to 200 angstroms.

5. The compound semiconductor device according to claim 4 , wherein the second silicide layer has a thickness ranging between 200 angstroms and 500 angstroms.

6. The compound semiconductor device according to claim 2 , wherein the first silicide layer comprises TiSi, the second silicide layer comprises TaSi, and the diffusion barrier comprises TaN.

7. The compound semiconductor device according to claim 1 , wherein the channel layer comprises GaN, wherein the buffer layer comprises AlN, AlGaN, or GaN.

8. The compound semiconductor device according to claim 1 , wherein the barrier layer comprises AlGaN.

9. The compound semiconductor device according to claim 1 , wherein the passivation layer comprises silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, or aluminum nitride.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Tsai Fu-Yu
• Tsai Bin-Siang
• Chiu Chung-Yi

Classifications

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title