Semiconductor device

Patent metadata

Field	Value
Publication number	US-12432972-B2
Application number	US-202217691680-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Jun 17, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A semiconductor device includes an active fin protruding from a substrate; a plurality of channel layers on the active fin and spaced apart from each other in a vertical direction; a gate pattern intersecting the active fin and the plurality of channel layers; and source/drain regions on recessed regions of the active fin on both sides of the gate pattern. The gate pattern includes a gate dielectric layer, inner conductive layers, and a conductive liner. The inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer among the plurality of channel layers. The conductive liner has a first thickness on an upper surface of an uppermost channel layer in the vertical direction, and at least one of the inner conductive layers have a second thickness in the vertical direction. The first thickness is less than the second thickness.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate having a first region and a second region;
a first active fin extending in a first direction in the first region of the substrate;
a plurality of first channel layers disposed on the first active fin and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate;
a first gate pattern intersecting the first active fin and the plurality of first channel layers on the substrate, extending in a second direction, and surrounding at least a portion of the plurality of first channel layers;
a second active fin extending in the first direction in the second region of the substrate;
a plurality of second channel layers disposed on the second active fin and spaced apart from each other in the vertical direction; and
a second gate pattern intersecting the second active fin and the plurality of second channel layers on the substrate, extending in the second direction, and surrounding at least a portion of the plurality of second channel layers,
wherein the first gate pattern comprises a first conductive layer, a first gate dielectric layer interposed between the first conductive layer and each of the plurality of first channel layers, and a second conductive layer on the first conductive layer,
wherein the first conductive layer and the first gate dielectric layer are disposed to fill spaces between the plurality of first channel layers,
wherein the first conductive layer comprises a liner portion disposed on an upper surface of an uppermost first channel layer from among the plurality of first channel layers and that has a first thickness in the vertical direction, and an inner portion disposed in the spaces between the plurality of first channel layers and that has a second thickness in the vertical direction, and
wherein the first thickness is less than 0.5 times the second thickness, and
wherein the semiconductor device further comprises first spacer layers disposed on both sides of the first gate pattern and extending in the second direction,
wherein the first gate dielectric layer conformally covers the upper surface of the uppermost first channel layer and inner side surfaces of the first spacer layers,
wherein the liner portion of the first conductive layer extends in the vertical direction along inner side surfaces of the first gate dielectric layer covering the inner side surfaces of the first spacer layers, wherein a thickness in the first direction of the liner portion on the inner side surfaces of the first gate dielectric layer is substantially equal to the first thickness, and
wherein the thickness in the first direction of the liner portion is a thickness between the inner side surfaces of the first gate dielectric layer and an interface that is present between the first conductive layer and an adjacent layer.

2. The semiconductor device of claim 1 , wherein the first conductive layer is in direct contact with the first gate dielectric layer,
wherein the second conductive layer is spaced apart from the inner portion of the first conductive layer, and
wherein the first thickness is a thickness of the liner portion in a central portion of the first gate pattern, and the second thickness is a thickness of the inner portion in the central portion of the first gate pattern.

3. The semiconductor device of claim 1 , wherein the liner portion of the first conductive layer extends below opposite side surfaces of the uppermost first channel layer in the second direction with a thickness in the second direction that is substantially equal to the first thickness.

4. The semiconductor device of claim 1 , wherein the second gate pattern comprises a third conductive layer, a second gate dielectric layer interposed between the third conductive layer and each of the plurality of second channel layers, and a fourth conductive layer on the third conductive layer,
wherein the third conductive layer, the fourth conductive layer, and the second gate dielectric layer are disposed to fill spaces between the plurality of second channel layers,
wherein the fourth conductive layer is disposed to surround the third conductive layer, and
wherein the third conductive layer is disposed between an upper surface of an uppermost second channel layer from among the plurality of second channel layers and a lower surface of the fourth conductive layer, at a higher level than the uppermost second channel layer, and the third conductive layer has a third thickness in the vertical direction that is less than the first thickness.

5. The semiconductor device of claim 4 , wherein the second thickness is greater than twice a difference between the first thickness and the third thickness.

6. The semiconductor device of claim 4 , wherein the first conductive layer, the second conductive layer, and the third conductive layer respectively comprise TiN, and the fourth conductive layer comprises TiAlC.

7. The semiconductor device of claim 1 , further comprising:
first source/drain regions disposed on the first active fin on both sides of the first gate pattern and connected to the plurality of first channel layers; and
second source/drain regions disposed on the second active fin on both sides of the second gate pattern and connected to the plurality of second channel layers,
wherein the first source/drain regions comprise a p-type impurity, and the second source/drain regions comprise an n-type impurity.

8. The semiconductor device of claim 7 , further comprising internal spacer layers disposed between the second source/drain regions and the second gate pattern in spaces between the plurality of second channel layers.

9. The semiconductor device of claim 7 , further comprising:
first contact structures connected to the first source/drain regions on the both sides of the first gate pattern; and
second contact structures connected to the second source/drain regions on the both sides of the second gate pattern.

10. The semiconductor device of claim 1 , wherein a width of at least one of the plurality of first channel layers in the second direction is different from a width of at least one of the plurality of second channel layers in the second direction.

11. A semiconductor device comprising:
an active fin protruding from a substrate and extending in a first direction;
a plurality of channel layers disposed on the active fin and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate;
a gate pattern intersecting the active fin and the plurality of channel layers on the substrate and extending in a second direction; and
source/drain regions disposed on recessed regions of the active fin on both sides of the gate pattern and connected to the plurality of channel layers,
wherein the gate pattern comprises a gate dielectric layer, inner conductive layers, and a conductive liner,
wherein the inner conductive layers are disposed between the plurality of channel layers, and between the active fin and a lowermost channel layer from among the plurality of channel layers,
wherein the gate dielectric layer is disposed between each of the inner conductive layers and each of the plurality of channel layers,
wherein the inner conductive layers and the conductive liner are in direct contact with the gate dielectric layer,
wherein the conductive liner extends from the inner conductive layers onto opposite side surfaces of the plurality of channel layers in the second direction and onto an upper surface of an uppermost channel layer, among the plurality of channel layers,
wherein the conductive liner has a first thickness on the upper surface of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaehyun
• LEE Jonghan
• Kang Hyungkoo
• Baek Jonghoon

Classifications

• H10D84/851

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/019

  of FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title