Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology

Patent metadata

Field	Value
Publication number	US-12432964-B2
Application number	US-202017030221-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a silicon (111) substrate having a first region and a second region;
a structure comprising gallium and nitrogen on the first region of the silicon (111) substrate, the structure comprising gallium and nitrogen having an uppermost surface and a bottommost surface;
a structure comprising germanium on the second region of the silicon (111) substrate, the structure comprising germanium having an uppermost surface co-planar with the uppermost surface of the structure comprising gallium and nitrogen, and the structure comprising germanium having a bottommost surface co-planar with the bottommost surface of the structure comprising gallium and nitrogen; and
a dielectric spacer laterally between and in contact with the structure comprising gallium and nitrogen and the structure comprising germanium, the dielectric spacer on the silicon (111) substrate, wherein the dielectric spacer has an uppermost surface co-planar with the uppermost surface of the structure comprising germanium and with the uppermost surface of the structure comprising gallium and nitrogen, and wherein the dielectric spacer has a bottommost surface co-planar with the bottommost surface of the structure comprising germanium and with the bottommost surface of the structure comprising gallium and nitrogen.

2. The semiconductor structure of claim 1 , wherein the structure comprising gallium and nitrogen comprises a polarization layer on a gallium nitride layer.

3. The semiconductor structure of claim 2 , wherein the polarization layer comprises AlGaN or InAlGaN.

4. The semiconductor structure of claim 1 , wherein the structure comprising gallium and nitrogen comprises a gallium nitride layer on an AlN layer.

5. The semiconductor structure of claim 1 , wherein the structure comprising germanium comprises a layer of SiGe on a layer of Ge.

6. The semiconductor structure of claim 1 , wherein the structure comprising germanium comprises a first layer of SiGe on a second layer of SiGe, the second layer of SiGe having a greater germanium concentration than the first layer of SiGe.

7. The semiconductor structure of claim 1 , wherein the dielectric spacer comprises silicon nitride or silicon oxide.

8. The semiconductor structure of claim 1 , wherein the structure comprising gallium and nitrogen has a first plurality of semiconductor devices thereon, the first plurality of semiconductor devices having a voltage supply in a range of 5-10 Volts, and wherein the structure comprising germanium has a second plurality of semiconductor devices thereon, the second plurality of semiconductor devices having a voltage supply of approximately 1 Volt.

9. The semiconductor structure of claim 8 , wherein the second plurality of semiconductor devices is a plurality of complementary metal oxide semiconductor (CMOS) devices.

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S
• Ehlert Robert
• Then Han Wui
• Radosavljevic Marko
• Thomas Nicole K
• Charue-Bakker Sandrine

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title