Semiconductor structure and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-12432940-B2
Application number	US-202217804178-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	Nov 4, 2021
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A method for manufacturing a semiconductor structure comprises: forming a stacked structure on a base having an array area and a peripheral area; forming a first mask layer on the stacked structure, in which the first mask layer corresponding to the array area has a first pattern; ion doping the first mask layer on the array area to obtain a doped first mask layer; and etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
forming a stacked structure on a base having an array area and a peripheral area;
forming a first mask layer on the stacked structure, wherein the first mask layer corresponding to the array area has a first pattern;
ion doping the first mask layer on the array area to obtain a doped first mask layer; and
etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure;
wherein
ion doping the first mask layer on the array area to obtain the doped first mask layer comprises:
depositing a sacrificial layer on the first mask layer and the part of the stacked structure;
etching the sacrificial layer on the array area to expose part of the first mask layer on the array area; and
ion doping the exposed first mask layer to obtain the doped first mask layer.

2. The method of claim 1 , wherein
forming the first mask layer on the stacked structure comprises:
forming a first initial mask layer and a second initial mask layer sequentially on the stacked structure, wherein the second initial mask layer is provided with the first pattern; and
etching the first initial mask layer through the second initial mask layer to transfer the first pattern into the first initial mask layer to form the first mask layer,
wherein the first mask layer exposes a surface of part of the stacked structure.

3. The method of claim 2 , further comprising:
removing the second initial mask layer after the first mask layer is formed.

4. The method of claim 2 , wherein
etching the sacrificial layer on the array area to expose the part of the first mask layer on the array area comprises:
forming a second mask layer on the sacrificial layer;
patterning the second mask layer to expose part of the sacrificial layer corresponding to the array area; and
etching the exposed part of the sacrificial layer to expose the part of the first mask layer.

5. The method of claim 4 , further comprising:
removing the second mask layer on the peripheral area and the remaining sacrificial layer to expose the first mask layer on the peripheral area after ion doping the exposed part of the first mask layer.

6. The method of claim 5 , wherein
an etching selectivity ratio of the doped first mask layer to the stacked structure is greater than an etching selectivity ratio of the first mask layer to the stacked structure.

7. The method of claim 4 , wherein
the first mask layer corresponding to the peripheral area is provided with a second pattern which has a pattern density less than a pattern density of the first pattern.

8. The method of claim 1 , wherein
the first pattern is a pattern of capacitor holes and the base is provided with a contact structure corresponding to the pattern of capacitor holes.

9. The method of claim 8 , wherein
the stacked structure comprises a first sacrificial layer, a first support layer, a second sacrificial layer and a second support layer stacked in sequence from bottom to top.

10. The method of claim 9 , wherein
etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure comprises:
etching the second support layer, the second sacrificial layer, the first support layer and the first sacrificial layer in sequence through the doped first mask layer to transfer the pattern of capacitor holes to the stacked structure, and forming a plurality of capacitor holes and etched pillars each between two adjacent capacitor holes in the stacked structure,
wherein the capacitor holes expose part of the contact structure.

11. The method of claim 10 , further comprising:
removing the first mask layer after the capacitor holes are formed.

12. The method of claim 11 , further comprising:
processing the etched pillars to form a capacitor structure.

13. The method of claim 12 , wherein
processing the etched pillars to form the capacitor structure comprises:
forming a first electrode layer on inner walls of the capacitor holes and on surfaces of the etched pillars;
forming a first opening in the second support layer;
removing the second sacrificial layer through the first opening;
forming a second opening in the first support layer;
removing the first sacrificial layer through the second opening; and
depositing a dielectric layer and a second electrode layer sequentially on a surface of the first electrode layer to form the capacitor structure.

Assignees

• Changxin Memory Tech Inc

Inventors

• Xia Jun
• Bai Shijie

Classifications

• H10D1/716

  having vertical extensions · CPC title

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title