Memory devices, operating methods of the memory devices, and test systems including the memory devices

Patent metadata

Field	Value
Publication number	US-12431209-B2
Application number	US-202318134776-A
Country	US
Kind code	B2
Filing date	Apr 14, 2023
Priority date	May 19, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.

First claim

What is claimed is:

1. A memory device comprising:
a decoder group configured to receive a plurality of codewords each including a plurality of symbols from an external device that is external of the memory device, the plurality of codewords including a plurality of normal codewords, and a plurality of illegal codewords which are mutually distinct, and configured to decode the plurality of normal codewords into a plurality of data patterns and the plurality of illegal codewords into a plurality of fixed patterns having an identical value;
a memory cell array configured to receive the plurality of data patterns and the plurality of fixed patterns from the decoder group and configured to store the plurality of data patterns and the plurality of fixed patterns, the memory cell array including a plurality of memory cells; and
an encoder configured to encode the plurality of data patterns read from the memory cell array into a plurality of first codewords and the plurality of fixed patterns read from the memory cell array into a plurality of second codewords having an identical value and to output the plurality of first codewords and the plurality of second codewords to the external of the memory device.

2. The memory device of claim 1 , wherein the plurality of symbols comprise 7 symbols, and each of the plurality of codewords are data including m bits, and each of the plurality of data patterns and the plurality of fixed patterns are data including n bits.

3. The memory device of claim 2 , wherein m and n are different positive integers, and m is greater than n.

4. The memory device of claim 2 , wherein the decoder group and the encoder are each configured to generate pulse amplitude modulation (PAM)-3 signals.

5. The memory device of claim 1 , wherein the decoder group comprises a first decoder, a second decoder, a third decoder, a fourth decoder, and a DFT logic, and the first decoder is configured to map each of the plurality of codewords with 2 bits 1 symbol, and the second through fourth decoders are configured to map each of the plurality of the codewords with 3 bits 2 symbols, and the first through fourth decoders are further configured to decode each of the plurality of codewords into corresponding one of the plurality of data patterns and the plurality of fixed patterns based on 11 bits 7 symbols mapping.

6. The memory device of claim 5 , wherein the DFT logic is configured to convert the plurality of illegal codewords into the plurality of fixed patterns.

7. The memory device of claim 5 , wherein a mapping table of the first decoder comprises 2 bits 1 symbol and invalid symbol, and mapping tables of the second through fourth decoders comprise unused symbol of 3 bits 2 symbols.

8. The memory device of claim 7 , wherein the DFT logic comprises:
a first OR circuit configured to receive the invalid symbol from the plurality of symbols included in each of the plurality of codewords, mapped by the first through fourth decoders to output a first value indicating whether each of the plurality of codewords includes the invalid symbol;
a second OR circuit configured to receive the unused symbol mapped by at least one second decoder, third decoder, and fourth decoder when the first decoder maps the invalid symbol, and to output a second value indicating whether each of the plurality of codewords includes the unused symbol; and
a third OR circuit configured to receive the first value of the first OR circuit and the second value of the second OR circuit and to output a third value indicating whether each of the plurality of codewords is the illegal codeword.

9. The memory device of claim 8 , wherein the DFT logic is further configured to convert the illegal codeword into the fixed pattern when the third OR circuit outputs the third value indicating each of the plurality of codewords is the illegal codeword.

10. An operating method of a memory device, the operating method comprising:
receiving a plurality of first codewords each including a plurality of symbols from a device that is external to the memory device, the plurality of first codewords including a plurality of normal codewords, and a plurality of illegal codewords which are mutually distinct;
decoding the plurality of normal codewords into a plurality of data patterns and the plurality of illegal codewords into a plurality of fixed patterns having an identical value;
storing the plurality of data patterns and the plurality of fixed patterns in a memory cell array;
reading the stored plurality of data patterns and the stored plurality of fixed patterns from the memory cell array; and
encoding the read plurality of data patterns the read plurality of fixed patterns into a plurality of second codewords,
wherein the encoding comprises encoding the read plurality of fixed patterns into corresponding second codewords having an identical value.

11. The operating method of claim 10 , further comprising outputting the plurality of second codewords to a device that is external to the memory device, wherein the plurality of second codewords are compared with the plurality of first codewords and used to test a status of the memory device.

12. The operating method of claim 10 , wherein the plurality of symbols comprise 7 symbols, and each of the plurality of first codewords are data including m bits, and each of the plurality of data patterns and the plurality of fixed patterns are data including n bits.

13. The operating method of claim 12 , wherein m and n are different positive integers, and m is greater than n.

14. The operating method of claim 10 , wherein the decoding and the encoding are based on a pulse amplitude modulation (PAM)-3 method.

15. The operating method of claim 10 , wherein the decoding of the plurality of normal codewords into the plurality of data patterns and the plurality of illegal codewords into the plurality of fixed patterns comprises:
a first operation in which each of the plurality of normal codewords and the plurality of illegal codewords is mapped with 2 bits 1 symbol;
a second operation in which each of the plurality of normal codewords and the plurality of illegal codewords is mapped with 3 bits 2 symbols;
a third operation in which each of the plurality of normal codewords and the plurality of illegal codewords is mapped with 3 bits 2 symbols; and
a fourth operation in which each of the plurality of normal codewords and the plurality of illegal codewords is mapped with 3 bits 2 symbols, and
each of the plurality of data patterns is decoded based on 11 bits 7 symbols mapping.

16. The operating method of claim 15 , wherein the plurality of symbols comprises an invalid symbol or an unused symbol.

17. The operating method of claim 15 , wherein the decoding the plurality of illegal codewords into the plurality of fixed patterns comprises:
receiving an invalid symbol from the plurality of symbols included in each of the plurality of first codewords;
receiving an unused symbol when the invalid symbol are mapped; and
outputting a value indicating whether a codeword including the invalid symbol or the unused symbol among the plurality of first codewords is the illegal codeword.

18. A test system comprising a memory device and a test device, wherein the memory device comprises:
a decoder group configured to receive a plurality of first codewords each including a plurality of symbols from of the test device, the plurality of first codewords including a plurality of normal codewords, and a plurality of illegal codewords which are mutually distinct, and to decode the plurality of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Wonyoung
• Kang Gilyoung
• Kim Sungrae
• Kim Hyeran
• Park Jeongseok
• Seol Changkyu

Classifications

• G11C29/38

  Response verification devices · CPC title

• G11C29/14

  Implementation of control logic, e.g. test mode decoders · CPC title

• H03M5/06

  Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell · CPC title

• G11C2029/5002

  Characteristic · CPC title

• G11C29/56008

  Error analysis, representation of errors · CPC title