Storage device that performs state shaping of data

Patent metadata

Field	Value
Publication number	US-11216338-B2
Application number	US-202016835721-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Jul 24, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2 m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2 m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile memory device including a plurality of pages, each of the plurality of pages including a plurality of memory cells; and
a controller configured to receive first write data expressed by 2 m states from an external host device,
wherein m is an integer greater than 1,
shape the first write data to second write data in a first operating mode, the second write data expressed by “k” states smaller in number than the 2 m states, wherein k is an integer greater than 2 and at least one of the 2 m states of the first write data is eliminated in the second write data,
perform first error correction encoding on the second write data to generate third write data expressed by the “k” states,
transmit the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages, and
store mapping information between patterns of the first write data and patterns of the second write data in a table, and shape the first write data to the second write data by using the table when the first write data are received.

2. The storage device of claim 1 , wherein the controller is configured to shape “i” bits of the first write data to “j” bits of the second write data,
wherein i is an integer greater than 2, j is an integer greater than 2, and “j” is greater than “i”.

3. The storage device of claim 1 , wherein the second write data include a value expressed by n-ary numbers, and n is an integer greater than 2, and
wherein each of the n-ary numbers is expressed by two or more bits.

4. The storage device of claim 3 , wherein in the second write data, at least one of combinations expressed by the two or more bits is eliminated.

5. The storage device of claim 1 , wherein in the second write data and the third write data, at least one of combinations of two or more bits is eliminated.

6. The storage device of claim 1 , wherein the controller further receives fourth write data together with the first write data, and the fourth write data include at least one page data expressed by at least two states at the plurality of memory cells, and
wherein the controller is further configured to perform second error correction encoding on the fourth write data to generate fifth write data, and transmit the fifth write data to the nonvolatile memory device for writing at the selected page together with the third write data.

7. The storage device of claim 6 , wherein the fourth write data include four page data expressed by 16 states at the plurality of memory cells, “m” is 2, and the first write data and the fourth write data are expressed by 64 states, and
wherein “k” is 3 and the plurality of memory cells of the selected page where the third write data and the fifth write data are written have 48 states.

8. The storage device of claim 6 , wherein the fourth write data include three page data expressed by 8 states at the plurality of memory cells, “m” is 2, and the first write data and the fourth write data are expressed by 32 states at the plurality of memory cells,
wherein the third write data are expressed by 3 states at the plurality of memory cells, and
wherein the plurality of memory cells of the selected page where the third write data and the fifth write data are written have 24 states.

9. The storage device of claim 6 , wherein the fourth write data include one page data expressed by 2 states at the plurality of memory cells, “m” is 3, and the first write data and the fourth write data are expressed by 16 states at the plurality of memory cells,
wherein the third write data are expressed by 7 states at the plurality of memory cells, and
wherein the plurality of memory cells of the selected page where the third write data and the fifth write data are written have 14 states.

10. The storage device of claim 6 , wherein the fourth write data include one page data expressed by 2 states at the plurality of memory cells, “m” is 2 , and the first write data and the fourth write data are expressed by 8 states at the plurality of memory cells,
wherein the third write data are expressed by 3 states at the plurality of memory cells, and
wherein the plurality of memory cells of the selected page where the third write data and the fifth write data are written have 6 states.

11. The storage device of claim 1 , wherein “m” is 2, and the third write data are expressed by 3 states at the plurality of memory cells.

12. The storage device of claim 1 , wherein “m” is 3, and the third write data are expressed by 7 states at the plurality of memory cells.

13. The storage device of claim 1 , wherein in a second operating mode, the controller is configured to perform second error correction encoding on the first write data to generate fourth write data, and transmit the fourth write data to the nonvolatile memory device for writing in the selected page.

14. The storage device of claim 13 , wherein in the first operating mode, the controller stores a flag indicating that the third write data are written through the first operating mode.

15. The storage device of claim 13 , wherein first voltages used by the nonvolatile memory device to write the transmitted third write data in the first operating mode are different from second voltages used by the nonvolatile memory device to write the fourth write data in the second operating mode.

16. A storage device comprising:
a nonvolatile memory device including a plurality of pages, each of the plurality of pages including a plurality of memory cells; and
a controller configured to
receive a read request from an external host device,
read first read data expressed by “k” states from a selected page from the plurality of pages of the nonvolatile memory device in response to the read request, wherein k is an integer greater than 2,
perform error correction decoding on the first read data to generate second read data expressed by the “k” states,
shape the second read data to third read data expressed by 2 m states greater in number than the “k” states, wherein m is an integer greater than 1 and the third read data includes at least one state that is not included in the second read data,
output the third read data to the external host device, and
store mapping information between patterns of the second read data and patterns of the third read data in a table, and shape the second read data to the third read data by using the table.

17. The storage device of claim 16 , wherein a number of bits of the second read data is more than a number of bits of the third read data.

18. A storage device comprising:
a nonvolatile memory device including a plurality of pages, each of the plurality of pages including a plurality of memory cells; and
a controller,
wherein the controller comprises
a host interface configured to receive first to sixth page data from an external host device,
a buffer configured to store the first to sixth page data transmitted from the host interface,
a binary error correction encoder configured to respectively perform error correction encoding on the first to fourth page data stored in the buffer to generate first to fourth encoded page data,
a shaping encoder configured to shape the fifth and sixth page data stored in the buffer to ternary data,
a ternary error correction encoder configured to perform ternary error correction encoding on the ternary data to generate ternary encoded data, and
a memory interface configured to transmit the first to fourth encoded page data and the ternary encoded data to th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Youngjun
• Shin Dong-Min
• Seol Changkyu
• Son Jaeyong
• Son Hong Rak

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title