Semiconductor device and data storage system including semiconductor device

Patent metadata

Field	Value
Publication number	US-12431195-B2
Application number	US-202318518496-A
Country	US
Kind code	B2
Filing date	Nov 23, 2023
Priority date	Dec 7, 2022
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first substrate structure including a first decoder circuit region, a second decoder circuit region, a page buffer circuit region between the first decoder circuit region and the second decoder circuit region, and a top surface facing in a first direction; and
a second substrate structure connected to the first substrate structure and on the top surface of the first substrate structure, wherein the second substrate structure includes:
a plate layer having a lower surface facing the top surface of the first substrate structure;
a first cell structure below the plate layer, the first cell structure including a plurality of first gate electrodes stacked on and spaced apart from each other in the first direction, a first side facing in a second direction perpendicular to the first direction, and a second side opposite the first side;
a second cell structure below the first cell structure, the second cell structure including a plurality of second gate electrodes stacked on and spaced apart from each other in the first direction, a first side facing in the second direction, and a second side opposite the first side;
a first stair structure adjacent to one of the first sides of the first and second cell structures, the first stair structure having portions of at least two of the first gate electrodes extending from the first cell structure to different lengths in the second direction;
a second stair structure adjacent to one of the second sides of the first and second cell structures, the second stair structure having portions of at least two of the second gate electrodes extending from the second cell structure to different lengths in the second direction;
a first dummy structure below the first stair structure, the first dummy structure having portions of the second gate electrodes extending in the second direction;
a plurality of first contact plugs passing through the first stair structure and the first dummy structure, the first contact plugs respectively connected to the at least two first gate electrodes; and
a plurality of second contact plugs passing through the second stair structure, the second contact plugs respectively connected to the at least two second gate electrodes, and
wherein the first stair structure overlaps the first decoder circuit region in the first direction, and the second stair structure overlaps the second decoder circuit region in the first direction.

2. The semiconductor device of claim 1 , wherein
the second substrate structure further includes a second dummy structure above the second stair structure, the second dummy structure having portions of at least one first gate electrode extending in the second direction, and
the second contact plugs pass through the second dummy structure.

3. The semiconductor device of claim 1 , wherein
each of the first and second decoder circuit regions includes a plurality of pass transistors,
at least one of the first gate electrodes is electrically connected to one of the pass transistors of the first decoder circuit region through one of the first contact plugs, and
at least one of the second gate electrodes is electrically connected to one of the pass transistors of the second decoder circuit region through one of the second contact plugs.

4. The semiconductor device of claim 1 , wherein the first decoder circuit region includes:
a plurality of pass transistors electrically connected to the first gate electrodes, respectively;
a first interconnection structure including circuit interconnection lines and a plurality of circuit contact plugs electrically connected to the pass transistors; and
a first bonding structure on the first interconnection structure, the first bonding structure including a plurality of first metal bonding pads.

5. The semiconductor device of claim 4 , wherein at least some of the first contact plugs are disposed to overlap the circuit contact plugs electrically connected thereto in the first direction.

6. The semiconductor device of claim 4 , wherein the second substrate structure further includes:
a second interconnection structure below the first and second contact plugs, the second interconnection structure including a plurality of circuit interconnection lines and a plurality of circuit contact plugs connected to the first and second contact plugs; and
a second bonding structure below the second interconnection structure, the second bonding structure including second metal bonding pads connected to the first metal bonding pads.

7. The semiconductor device of claim 1 , wherein lower surfaces of the first and second contact plugs are coplanar.

8. The semiconductor device of claim 1 , wherein upper ends of the first and second contact plugs extend into the plate layer.

9. The semiconductor device of claim 1 , wherein each of the first contact plugs has a bent portion between the first stair structure and the first dummy structure.

10. The semiconductor device of claim 1 , wherein the second substrate structure further includes:
a third cell structure spaced apart from the first stair structure in the second direction, the third cell structure including a plurality of third gate electrodes stacked on and spaced apart from each other in the first direction;
a fourth cell structure below the third cell structure, the fourth cell structure including a plurality of fourth gate electrodes stacked on and spaced apart from each other in the first direction; and
a third stair structure between the first stair structure and the third cell structure, the third stair structure having portions of at least three of the third gate electrodes extending from the third cell structure to different lengths in the second direction.

11. The semiconductor device of claim 10 , wherein
the second substrate structure further includes a third dummy structure below the third stair structure, the third dummy structure having portions of the fourth gate electrodes extending in the second direction, and
the second gate electrodes are each connected to one of the fourth gate electrodes between the first dummy structure and the third dummy structure.

12. The semiconductor device of claim 10 , wherein the second substrate structure further includes a connection structure connecting the first gate electrodes and the third gate electrodes to each other, and respectively connecting the second gate electrodes and the fourth gate electrodes to each other.

13. The semiconductor device of claim 10 , wherein the first stair structure and the third stair structure have different stair structure slopes.

14. The semiconductor device of claim 1 , wherein a stair structure height of the first stair structure is different from a stair structure height of the second stair structure.

15. The semiconductor device of claim 1 , wherein
the second substrate structure further includes channel structures passing through the first and second cell structures, and
lower ends of the channel structures are coplanar with level of lower ends of the first and second contact plugs.

16. A semiconductor device comprising:
a first substrate structure including a first decoder circuit region, a second decoder circuit region, a page buffer circuit region between the first decoder circuit region and the second decoder circuit region, and a top surface facing in a vertical direction; and
a second substrate structure connected to the first substrate structure and disposed on the first substrate structure,
wherein the second substrate structure includes:
a first cell structure including

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jiwon
• Kim Jiyoung
• Yang Woosung
• Kim Dohyung
• Sung Sukkang

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W90/792

  between multiple chips · CPC title