Vertical memory device including common source line structure

Patent metadata

Field	Value
Publication number	US-10964638-B2
Application number	US-201916704499-A
Country	US
Kind code	B2
Filing date	Dec 5, 2019
Priority date	Jan 28, 2016
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

First claim

What is claimed is:

1. An integrated circuit (IC) device comprising:
a peripheral circuit on a substrate;
a semiconductor layer on the peripheral circuit;
a memory cell array region on the semiconductor layer and overlapping the peripheral circuit in a vertical direction, the memory cell array region comprising a plurality of memory cell arrays and a common source line tab region between adjacent two of the plurality of memory cell arrays;
a plurality of word lines that extend on the semiconductor layer, parallel to a main surface of the substrate, and are included in each of the plurality of memory cell arrays and separated from one another in a first direction perpendicular to the main surface of the substrate;
a plurality of channel regions that extend on the semiconductor layer in the first direction, passing through the plurality of word lines;
a plurality of bit line contact pads that are on the plurality of channel regions to contact the plurality of channel regions;
a plurality of bit lines that extend in a region separated from the common source line tab region, in a second direction parallel to the main surface of the substrate and contact a plurality of bit line contact pads;
a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height lower than that of the plurality of channel regions;
at least one common source via contact that contacts an upper surface of the common source line in the common source line tab region and extends from the upper surface of the common source line in a direction away from the substrate;
a plurality of dummy channel regions that extend in the first direction, penetrating the plurality of word lines in the common source line tab region; and
a plurality of dummy contact pads that are formed on the plurality of dummy channel regions to contact upper surfaces of the plurality of dummy channel regions.

2. An integrated circuit (IC) device comprising:
a peripheral circuit on a substrate;
a semiconductor layer on the peripheral circuit;
a memory cell array region on the semiconductor layer and overlapping the peripheral circuit in a vertical direction, the memory cell array region comprising a plurality of memory cell arrays and a common source line tab region between adjacent two of the plurality of memory cell arrays;
a plurality of word lines that extend on the semiconductor layer, parallel to a main surface of the substrate, and are included in each of the plurality of memory cell arrays and separated from one another in a first direction perpendicular to the main surface of the substrate;
a plurality of channel regions that extend on the semiconductor layer in the first direction, passing through the plurality of word lines;
a plurality of bit line contact pads that are on the plurality of channel regions to contact the plurality of channel regions;
a plurality of bit lines that extend in a region separated from the common source line tab region, in a second direction parallel to the main surface of the substrate and contact a plurality of bit line contact pads;
a common source line that partially fills a word line cut region, the word line cut region extending in a third direction on a side of the plurality of word lines, the third direction being parallel to the main surface of the substrate and intersecting the second direction, the common source line having a height lower than that of the plurality of channel regions;
at least one common source via contact that contacts an upper surface of the common source line in the common source line tab region and extends from the upper surface of the common source line in a direction away from the substrate;
an upper insulating layer that extends to cover the plurality of bit lines and has at least one contact hole through which the at least one common source via contact penetrates;
a first upper wiring layer that covers the plurality of bit lines with the upper insulating layer interposed therebetween; and
a second upper wiring layer that is formed at a level the same as that of the first upper wiring layer in the common source line tab region and is connected to the at least one common source via contact.

3. An integrated circuit (IC) device comprising:
at least one ground select line, a plurality of word lines, and at least one string select line sequentially stacked on a substrate, extending parallel to a main surface of the substrate and being spaced apart from one another with an insulating layer interposed between each separation in a first direction perpendicular to the main surface;
a channel region extending in a first region on the substrate through the at least one ground select line, the plurality of word lines, and the at least one string select line;
a dummy channel region extending in a second region separated from the first region on the substrate through the at least one ground select line, the plurality of word lines, and the at least one string select line;
a bit line contact pad deposited on the channel region and contacting an upper surface of the channel region;
a bit line contacting the bit line contact pad in the first region and extending on the bit line contact pad in a second direction parallel to the main surface of the substrate;
a common source line partially filling a word line cut region, the word line cut region extending in a third direction on a side of the at least one ground select line, the plurality of word lines, and the at least one string select line, the third direction being parallel to the main surface of the substrate and intersecting the second direction;
a word line cut region buried insulating layer deposited on the common source line in the word line cut region to fill up the word line cut region;
a common source via contact surrounded by the word line cut region buried insulating layer, contacting an upper surface of the common source line in the word line cut region and extending from the upper surface of the common source line in a direction away from the substrate in the second region;
a first upper wiring layer covering the bit line in the first region with an upper insulating layer interposed therebetween; and
a second upper wiring layer formed at a level the same as that of the first upper wiring layer in the second region and being connected to the common source via contact.

4. The IC device of claim 3 , wherein the common source line has a height lower than a height of the channel region, and the height of the common source line is less than two thirds (⅔) of a total height of the word line cut region.

5. The IC device of claim 4 , wherein the height of the common source line is less than one half (½) of the total height of the word line cut region.

6. The IC device of claim 3 , wherein material of the common source line includes tungsten.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kwang-Soo

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D1/00 Primary

  Resistors, capacitors or inductors · CPC title

• H01L27/115

  Electricity · mapped topic

• H01L23/5226 Primary

  Electricity · mapped topic