Efficient signaling scheme for high-speed ultra short reach interfaces

US12430268B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12430268-B2
Application numberUS-202519016446-A
CountryUS
Kind codeB2
Filing dateJan 10, 2025
Priority dateMar 28, 2016
Publication dateSep 30, 2025
Grant dateSep 30, 2025

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  5. First independent claim

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Abstract

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A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

First claim

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We claim: 1. A semiconductor device package, comprising: a multi-chip module (MCM) comprising: a common chip package substrate; a first group of integrated circuit (IC) chips coupled to the common chip package substrate; a second group of IC chips coupled to the common chip package substrate; and a transfer IC chip coupled to the common chip package substrate and packaged with the first group of IC chips and the second group of IC chips to form a unitary IC chip package, the transfer IC chip communicatively interposed between the first group of IC chips and the second group of IC chips, the transfer IC chip configured as a repeater to transfer a first signal from a first IC chip of the first group of IC chips to a second IC chip of the second group of IC chips and transfer a second signal from the first IC chip to an output interface, the output interface configured to output the signals from the MCM; a first set of ultra short reach (USR) signaling links to connect the first group of IC chips to the transfer IC chip; a second set of USR signaling links to connect the second group of IC chips to the transfer IC chip; and wherein each of the first set of USR signaling links and each of the second set of USR signaling links comprises a trace length of less than one inch. 2. The semiconductor device package of claim 1 , wherein: each of the first set of USR signaling links and each of the second set of USR signaling links comprises a simultaneously bidirectional signaling link. 3. The semiconductor device package of claim 1 , wherein: the common chip package substrate is formed with a mounting surface having a first side and a second side located opposite the first side; wherein the first group of IC chips is mounted on the first side of the common chip package substrate; and wherein the second group of IC chips is mounted on the second side of the common chip package substrate. 4. The semiconductor device package of claim 1 , wherein: the first group of IC chips, the second group of IC chips and the transfer IC chip are mounted to the common chip package substrate in a planar configuration. 5. The semiconductor device package of claim 1 , wherein: the transfer IC chip comprises switching circuitry to forward the first signal from the first IC chip of the first group of IC chips to the second IC chip of the second group of IC chips and transfer the second signal from the first IC chip to the output interface. 6. A semiconductor device package, comprising: a multi-chip module (MCM) comprising: a common chip package substrate; a first group of IC chips coupled to the common chip package substrate and comprising a first integrated circuit (IC) chip to transmit first data off the first IC chip; and a transfer IC chip coupled to the common chip package substrate in a planar configuration with the first group of IC chips, the transfer IC chip packaged with the first group of IC chips, the transfer IC chip to receive the first data from the first IC chip via at least one first link, the transfer IC chip, configured as a repeater, comprising switching circuitry to selectively forward the first data to one of a first output interface and a second output interface, the first output interface communicatively coupled to a third IC chip of a second group of IC chips via at least one second link, the second group of IC chips being coupled to the common chip package substrate in a planar configuration with the first group of IC chips and the transfer IC chip, the second output interface configured to output the first data from the MCM; wherein the at least one first link further comprises a first set of ultra short reach (USR) signaling links to connect the first group of IC chips to the transfer IC chip; and the at least one second link further comprises a second set of USR signaling links to connect the second group of IC chips to the transfer IC chip; wherein each of the first set of USR signaling links and each of the second set of USR signaling links comprises a trace length of less than one inch. 7. The semiconductor device package of claim 6 , wherein the transfer IC chip further comprises: on-chip conductors to supply the first data on-chip to the switching circuitry. 8. The semiconductor device package of claim 6 , wherein: the second output interface comprises a serial data port to communicate with a serial link. 9. The semiconductor device package of claim 6 , wherein: each of the first set of USR signaling links and each of the second set of USR signaling links comprises a simultaneously bidirectional signaling link. 10. The semiconductor device package of claim 6 , wherein: the common chip package substrate is formed with a mounting surface having a first side and a second side located opposite the first side; wherein the first group of IC chips is mounted on the first side of the common chip package substrate; and wherein the second group of IC chips is mounted on the second side of the common chip package substrate. 11. A semiconductor device, comprising: a chip package substrate; and a first integrated circuit (IC) chip coupled to the chip package substrate to receive first data, the first IC chip to package in a multi-chip module (MCM) with a first group of IC chips and a second group of IC chips, the first IC chip comprising an input interface to receive the first data from the first group of IC chips via at least one first link, the first IC chip configured to mount to the chip package substrate in a planar orientation with the first group of IC chips and the second group of IC chips, the first IC chip, configured as a repeater, comprising switching circuitry to selectively forward the first data to one of a first output interface and a second output interface, the first output interface to couple to the second group of IC chips via at least one second link, the second output interface configured to output the first data from the MCM; wherein the at least one first link further comprises a first set of ultra short reach (USR) signaling links to connect the first group of IC chips to the first IC chip; and the at least one second link further comprises a second set of USR signaling links to connect the second group of IC chips to the first IC chip, wherein each of the first set of USR signaling links and each of the second set of USR signaling links comprises a trace length of less than one inch. 12. The semiconductor device of claim 11 , wherein: the first IC chip comprises on-chip conductors to supply the first data on-chip from the input interface to the switching circuitry. 13. The semiconductor device of claim 11 , wherein: the second output interface comprises a serial data port to communicate with a serial link.

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What does patent US12430268B2 cover?
A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of I…
Who is the assignee on this patent?
Marvell Aisa Pte Ltd, Marvell Asia Pte Ltd
What technology area does this patent fall under?
Primary CPC classification G06F13/36. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).