Receiver with pipelined tap coefficients and shift control

Patent metadata

Field	Value
Publication number	US-9294313-B2
Application number	US-201414146920-A
Country	US
Kind code	B2
Filing date	Jan 3, 2014
Priority date	Jan 3, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

First claim

We claim:

1. An apparatus comprising:
a plurality of signal processing blocks configured to serially process a digitized input data stream, each block having a data input, a data output coupling to an input of a subsequent signal processing block, and a coefficient input;
a plurality of coefficient delay elements, each coefficient delay element having a control input, a coefficient input, a coefficient output coupling to a coefficient input of a subsequent coefficient delay element and to the coefficient input of a corresponding one of the signal processing blocks;
a shift register having an input and a plurality of outputs, the plurality of outputs coupled to the control inputs of corresponding ones of the coefficient delay elements; and
an adaptation unit, having an input coupled to the data output of a last one of the signal processing blocks, a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements;
wherein the adaptation unit generates a flag on the flag output when the adaptation unit generates a coefficient, the flag is entered into the shift register and, in response, the generated coefficient is entered into the first one of the coefficient delay elements.

2. The apparatus of claim 1 wherein the shift register has at least as many outputs as there are coefficient delay elements and is configured to shift the flag through the shift register in response to a clock signal such that, when the flag appears at an output of the shift register, the coefficient delay element corresponding to that shift register output transfers data to its output from its preceding coefficient delay element.

3. The apparatus of claim 2 , wherein each of the signal processing blocks has a processing delay, and the shift register is configured to cause each coefficient delay element to hold the coefficient therein for substantially as long as the processing delay of the corresponding the signal processing block.

4. The apparatus of claim 3 , wherein the shift register comprises a plurality of serially-coupled flip-flops responsive to a common clock, each one of the plurality of outputs being from one of the serially-coupled flip-flops, the amount of delay between outputs of the shift register being a function of a number of flip-flops disposed between flip-flops having outputs coupled to the coefficient delay elements.

5. The apparatus of claim 2 further comprising:
a plurality of serially-coupled delay blocks, each delay block corresponding to a signal processing block;
wherein a first one of the delay blocks receives the digitized data stream, and an output of a last one of the delay blocks is coupled to the adaptation unit.

6. The apparatus of claim 5 wherein each of the serially-coupled delay blocks has a control input coupled to the control inputs of corresponding ones of the coefficient delay elements.

7. The apparatus of claim 5 wherein each of the signal processing blocks has a processing delay, and each delay block providing a delay substantially equal to the processing delay of the corresponding signal processing block.

8. The apparatus of claim 5 further comprising:
a error generator, disposed between the last one of the signal processing blocks and the input of the adaptation block, and coupled to the output of the last one of the delay blocks.

9. The apparatus of claim 8 further comprising:
an analog-to-digital converter configured to digitize an input signal to form the digitized input data stream.

10. The apparatus of claim 9 further comprising:
an additional signal processor block, disposed between the analog-to-digital converter and the plurality of signal processor blocks, having a coefficient input; and
an additional delay block disposed between analog-to-digital converter and the first delay block;
wherein the adaptation unit has a second coefficient output, the second coefficient output coupled to the coefficient input of the additional signal processor block.

11. The apparatus of claim 10 , wherein the additional signal processor unit is a feed-forward equalizer, the first one of the signal processing blocks is a decision-feedback equalizer, the last one of the signal processing blocks being an intersymbol interference processor, and remaining signal processor blocks being decision feed-forward equalizers.

12. The apparatus of claim 1 , wherein the apparatus is embodied in a serializer-deserializer (SERDES) device.

13. The apparatus of claim 1 wherein the apparatus is disposed in an integrated circuit.

14. A method, comprising:
serially processing a digitized input data stream with a plurality of signal processing blocks, each block having a data input, a data output coupling to an input of a subsequent signal processing block, and a coefficient input;
coupling a plurality of coefficient delay elements to a corresponding one of the signal processing blocks, wherein each coefficient delay element comprises a control input, a coefficient input, and a coefficient output coupling to a coefficient input of a subsequent coefficient delay element as well as the coefficient input of the corresponding one of the signal processing blocks;
coupling a shift register to the control inputs of corresponding one of the coefficient delay elements, wherein the shift register comprises an input and a plurality of outputs, the plurality of outputs being coupled to the control inputs of the corresponding ones of the coefficient delay elements;
coupling an input of an adaptation unit to the data output of a last one of the signal processing blocks, the adaptation unit further comprising a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay element; and
generating a flag with the adaptation unit on the flag output when the adaptation unit generates a coefficient, the flag being entered into the shift register and, in response, the generated coefficient being entered into the first one of the coefficient elements.

15. The method of claim 14 , wherein the shift register has at least as many outputs as there are coefficient delay elements and is configured to shift the flag through the shift register in response to a clock signal such that, when the flag appears at an output of the shift register, the coefficient delay element corresponding to that shift register output transfers data to its output from its preceding coefficient delay element.

16. The method of claim 15 , wherein each of the signal processing blocks has a processing delay, and the shift register is configured to cause each coefficient delay element to hold the coefficient therein for substantially as long as the processing delay of the corresponding the signal processing block.

17. The method of claim 16 , wherein the shift register comprises a plurality of serially-coupled flip-flops responsive to a common clock, each one of the plurality of outputs being from one of the serially-coupled flip-flops, the amount of delay between outputs of the shift register being a function of a number of flip-flops disposed between flip-flops having outputs coupled to the coefficient delay elements.

18. The method of claim 15 , further comprising:
receiving the digitized data stream with a first one of a plurality of serially-coupled delay blocks, each delay block corresponding to a signal processing block, and wherein an output of a last one of the delay blocks is coupled to the adaptation unit.

Assignees

• Lsi Corp
• Avago Technologies General Ip

Inventors

• Prokop Tomasz
• Shvydun Volodmyr
• Annampedu Viswanath
• Malipatil Amaresh V

Classifications

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03535

  Variable structures · CPC title