Memory controller for controlling communication with host and method of operating the same

Patent metadata

Field	Value
Publication number	US-12430244-B2
Application number	US-202318470054-A
Country	US
Kind code	B2
Filing date	Sep 19, 2023
Priority date	Apr 10, 2023
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

The present technology relates to an electronic device. According to the present technology, a memory controller may include a garbage collection controller and a sustain detector. The garbage collection controller may generate garbage collection information including valid page count values of victim memory blocks on which garbage collection is to be performed among a plurality of memory blocks included in a memory device. The sustain detector in communication with the garbage collection controller may generate sustain information indicating whether random write performance for the memory device is in a sustain state in which a random write performance value related to a capability of the random write performance is greater than or equal to a threshold value based on the garbage collection information.

First claim

What is claimed is:

1. A memory controller, comprising:
a garbage collection controller configured to generate garbage collection information including valid page count values of victim blocks on which garbage collection is to be performed among a plurality of memory blocks included in a memory device;
a sustain detector in communication with the garbage collection controller and configured to generate sustain information indicating whether random write performance for the memory device is in a sustain state in which a random write performance value related to a capability of the random write performance is greater than or equal to a threshold value based on the garbage collection information; and
a write controller configured to control a latency of a response to a request received from a host based on the sustain information.

2. The memory controller of claim 1 , wherein the write controller is configured to perform write throttling that delays the latency of the response in response to the memory device being in the sustain state.

3. The memory controller of claim 1 , wherein the sustain detector is configured to generate the sustain information and provide the sustain information to a host whenever the garbage collection is performed.

4. The memory controller of claim 1 , wherein the sustain detector is configured to determine whether the memory device is in the sustain state based on whether a check value is within a preset range, the check value being an average of valid page count values of the victim blocks.

5. The memory controller of claim 4 , wherein the sustain detector is configured to determine that the memory device is in the sustain state in response to the check value being within the preset range that is greater than or equal to a first reference value and less than a second reference value.

6. The memory controller of claim 5 , wherein the first reference value is a minimum value of valid page count values of victim blocks that are set in a manufacturing process, and
the second reference value is a maximum value of the valid page count values of the victim blocks.

7. The memory controller of claim 1 , wherein the sustain detector is configured to determine whether the memory device is in the sustain state based on a plurality of check values corresponding to a plurality of groups including different numbers of victim blocks, and
each of the plurality of check values is an average of valid page count values of victim blocks belonging to a corresponding group.

8. The memory controller of claim 7 , wherein the sustain detector is configured to determine that the memory device is in the sustain state in response to a standard deviation of the plurality of check values being less than or equal to a reference deviation.

9. The memory controller of claim 7 , wherein the sustain detector is configured to determine that the memory device is in the sustain state in response to an error between each of the plurality of check values and an average of the plurality of check values being less than or equal to a reference error.

10. The memory controller of claim 7 , wherein the sustain detector preferentially allocate a victim block having a valid page count value lower than that of another victim block among the victim blocks to the plurality of groups.

11. The memory controller of claim 1 , wherein the sustain information indicates any one of the sustain state in which the garbage collection is being executed and the random write performance value is greater than or equal to the threshold value, a transition state in which the garbage collection is being executed and the random write performance value is less than the threshold value, and a no-transition state in which the garbage collection is not executed.

12. A method of operating a memory controller, the method comprising:
calculating, by the memory controller, valid page count values of victim blocks on which garbage collection is to be performed among a plurality of memory blocks included in a memory device;
performing the garbage collection on the victim blocks;
generating sustain information indicating whether a random write performance for the memory device is in a sustain state, based on valid page count values of the victim blocks;
providing the sustain information to a host; and
performing write throttling that delays a latency of a response to a request received from the host when the memory device is in the sustain state.

13. The method of claim 12 , wherein generating the sustain information comprises:
calculating a check value that is an average of the valid page count values of the victim blocks; and
determining whether the memory device is in the sustain state based on whether the check value falls within a preset range.

14. The method of claim 13 , wherein determining whether the memory device is in the sustain state comprises determining that the memory device is in the sustain state when the check value is greater than or equal to a first reference value and less than a second reference value as the preset range,
the first reference value is a minimum value of the valid page count values of the victim blocks set in a manufacturing process of the memory device, and
the second reference value is a maximum value of the valid page count values of the victim blocks set in the manufacturing process.

15. The method of claim 12 , wherein generating the sustain information comprises:
allocating different numbers of victim blocks among the victim blocks to each of a plurality of groups; and
determining whether the memory device is in the sustain state based on a plurality of check values corresponding to the plurality of respective groups, and
each of the plurality of check values is an average of valid page count values of victim blocks belonging to a corresponding group.

16. The method of claim 12 , wherein the sustain information indicates any one of the sustain state in which the garbage collection is being executed and a random write performance value related to a capability of the random write performance is greater than or equal to a threshold value, a transition state in which the garbage collection is being execute and the random write performance value is less than the threshold value, and a no-transition state in which the garbage collection is not executed.

17. A storage device, comprising:
a memory device including a plurality of memory blocks, each memory block including a plurality of pages configured to store data; and
a memory controller in communication with the memory device and configured to select victim blocks on which garbage collection is to be performed among the plurality of memory blocks, calculate valid page count values of the victim blocks, generate sustain information indicating whether random write performance for the plurality of memory blocks is in a sustain state in which a random write performance value related to a capability of the random write performance is greater than or equal to a threshold value based on the valid page count values, and control a response latency of a request received from a host based on the sustain information.

18. The storage device of claim 17 , wherein the memory controller is configured to provide the sustain information to the host.

Assignees

• Sk Hynix Inc

Inventors

• Song In Sung
• Koo Dong Hwan
• Kim Ki Tae
• Kim Chan Sik
• Seo Dong Young
• Shin Woong Sik
• Jung In Ho
• Heo Jae Hoon

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title