Sharing register file usage between fused processing resources

Patent metadata

Field	Value
Publication number	US-12430128-B2
Application number	US-202217569229-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Sep 25, 2019
Publication date	Sep 30, 2025
Grant date	Sep 30, 2025

Abstract

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to:
receive an instruction to initiate a matrix multiplication operation;
cause a first memory arbiter to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to a first processing resource by a first data bus and a second processing resource by a second data bus;
share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation, wherein the first and second processing resources are fused and associated with the processor circuitry; and
facilitate storing of the first output and the second output in a third set of registers.

2. The apparatus of claim 1 , wherein the processor circuitry is further to:
allocate a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

3. The apparatus of claim 1 , wherein the processor circuitry is further to:
cause a second memory arbiter to write a second set of matrix data into a second set of registers.

4. The apparatus of claim 1 , wherein the processor circuitry is further to:
generate a signal to execute the matrix multiplication operation based on the first set of matrix data and the second set of matrix data associated with the first processing resource and the second processing resource, respectively.

5. The apparatus of claim 4 , wherein:
the first processing resource generates a first output representing a first matrix multiplication relating to the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output representing a second matrix multiplication relating to the second portion of the first set of matrix data and the second set of matrix data.

6. The apparatus of claim 5 , wherein the processor circuitry comprises one or more of graphics processor circuitry or application processor circuitry.

7. At least one non-transitory computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
receiving an instruction to initiate a matrix multiplication operation;
causing a first memory arbiter to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to a first processing resource by a first data bus and a second processing resource by a second data bus;
sharing the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation, wherein the first and second processing resources are fused and associated with a processor of the computing device; and
facilitating storing of the first output and the second output in a third set of registers.

8. The non-transitory computer-readable medium of claim 7 , wherein the operations further comprise:
allocating a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

9. The non-transitory computer-readable of claim 7 , wherein the operations further comprise:
causing a second memory arbiter to write a second set of matrix data into a second set of registers.

10. The non-transitory computer-readable of claim 7 , wherein the operations further comprise:
generate a signal to execute the matrix multiplication operation based on the first set of matrix data and the second set of matrix data associated with the first processing resource and the second processing resource, respectively.

11. The non-transitory computer-readable of claim 10 , wherein:
the first processing resource generates a first output representing a first matrix multiplication relating to the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output representing a second matrix multiplication relating to the second portion of the first set of matrix data and the second set of matrix data.

12. The non-transitory computer-readable medium of claim 11 , wherein the processor comprises one or more of a graphics processor or an application processor.

13. A method comprising:
receiving, by a processor of a computing device, an instruction to initiate a matrix multiplication operation;
causing a first memory arbiter to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to a first processing resource by a first data bus and a second processing resource by a second data bus;
sharing the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation, wherein the first and second processing resources are fused and associated with the processor; and
facilitating storing of the first output and the second output in a third set of registers.

14. The method of claim 13 , further comprising:
allocating a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

15. The method of claim 13 , further comprising:
causing a second memory arbiter to write a second set of matrix data into a second set of registers.

16. The method of claim 13 , further comprising:
generating a signal to execute the matrix multiplication operation based on the first set of matrix data and the second set of matrix data associated with the first processing resource and the second processing resource, respectively.

17. The method of claim 16 , wherein:
the first processing resource generates a first output representing a first matrix multiplication relating to the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output representing a second matrix multiplication relating to the second portion of the first set of matrix data and the second set of matrix data.

18. The method of claim 17 , wherein the processor comprises one or more of a graphics processor or an application processor.

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• George Varghese
• Ray Joydeep
• Garg Ashutosh
• Parra Jorge
• Shah Shubh
• Marwaha Shubra

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06N3/045

  Combinations of networks · CPC title