Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Patent metadata

Field	Value
Publication number	US-12426342-B2
Application number	US-202117359327-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor channel;
a gate stack over the semiconductor channel;
a source region on a first end of the semiconductor channel;
a drain region on a second end of the semiconductor channel; and
a barrier layer over the source region, wherein the barrier layer comprises titanium, silicon, germanium, and boron throughout an entirety of the barrier layer.

2. The semiconductor device of claim 1 , wherein an atomic percentage of silicon is greater than an atomic percentage of germanium in the single material layer.

3. The semiconductor device of claim 1 , wherein a concentration of silicon in the barrier layer is greatest at an interface between the source region and the barrier layer.

4. The semiconductor device of claim 1 , wherein the source region comprises silicon germanium.

5. The semiconductor device of claim 1 , wherein an atomic percentage of germanium in the barrier layer proximate to the interface between the source region and the barrier layer is approximately 15 percent or lower.

6. The semiconductor device of claim 1 , wherein the semiconductor device is configured to have a contact resistance between the source region and the barrier layer is approximately 2e −9 ohm·cm 2 or lower.

7. An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises a transistor device, wherein the transistor device comprises:
a semiconductor channel;
a gate stack over the semiconductor channel;
a source region on a first end of the semiconductor channel;
a drain region on a second end of the semiconductor channel; and
a barrier layer over the source region, wherein the barrier layer comprises titanium, silicon, germanium, and boron throughout an entirety of the barrier layer.

8. The electronic system of claim 7 , wherein the transistor device is a fin-FET transistor or a gate-all-around (GAA) transistor.

Assignees

• Intel Corp

Inventors

• Nandi Debaleena
• Bomberger Cory
• Dewey Gilbert
• Murthy Anand S
• Kobrinsky Mauro
• Shah Rushabh
• Choi Chi-Hing
• Kennel Harold W
• Saadat Omair
• Oni Adedapo A
• Haratipour Nazila
• Ghani Tahir

Classifications

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title