Semiconductor structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12426283-B2
Application number	US-202217816242-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Jul 29, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A semiconductor structure includes a recess extending into a substrate and an inductor device including a first isolation layer, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, and a conductive element surrounded by the second isolation layer, wherein at least a portion of the inductor device is disposed within the recess. A method of manufacturing a semiconductor structure includes disposing a first isolation layer on a surface of a substrate and extending into a recess formed on the surface; disposing a first magnetic layer over the first isolation layer; disposing a second isolation layer over the first magnetic layer to form a trench; disposing a conductive element in the trench; disposing a third isolation layer over the first magnetic layer, the conductive element and the second isolation layer; and disposing a second magnetic layer over the third isolation layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate including a surface;
a recess extending into the substrate from the surface of the substrate; and
an inductor device including a first isolation layer, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, a conductive element surrounded by the second isolation layer, and a third isolation layer disposed over the second isolation layer and the conductive element, and a second magnetic layer disposed over the third isolation layer,
wherein at least a portion of the inductor device is disposed within the recess, and a portion of the third isolation layer is exposed by the second magnetic layer.

2. The semiconductor structure of claim 1 , wherein the first isolation layer is disposed within the recess and conformal to the recess, and the first magnetic layer is conformal to the first isolation layer.

3. The semiconductor structure of claim 1 , wherein at least a portion of the first magnetic layer is disposed within the recess.

4. The semiconductor structure of claim 1 , wherein the second isolation layer is disposed between the conductive element and the first magnetic layer.

5. The semiconductor structure of claim 1 , wherein at least a portion of the conductive element is disposed within the recess.

6. The semiconductor structure of claim 1 , wherein the third isolation layer is disposed over the conductive element and the first magnetic layer.

7. The semiconductor structure of claim 1 , wherein the first isolation layer includes a main portion disposed within the recess and an extension portion attached to the main portion and disposed on the surface of the substrate.

8. The semiconductor structure of claim 1 , wherein a top surface of the conductive element is level with the first magnetic layer.

9. The semiconductor structure of claim 3 , wherein the third isolation layer and the second magnetic layer are disposed over the substrate, and the third isolation layer covers the conductive element and the second isolation layer.

10. The semiconductor structure of claim 1 , wherein the third isolation layer contacts the second isolation layer.

11. A semiconductor structure, comprising:
a substrate having a first recess on a surface and a second recess adjacent to the first recess;
a first inductor device; and
a second inductor device adjacent to the first inductor device and electrically connected to the first inductor device;
wherein the first inductor device includes a first isolation layer conformal to the first recess, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, and a first conductive element within the first recess and surrounded by the first magnetic layer and the second isolation layer,
wherein the second inductor device includes a third isolation layer conformal to the second recess, a second magnetic layer over the third isolation layer, a fourth isolation layer over the second magnetic layer, and a second conductive element within the second recess and surrounded by the second magnetic layer and the fourth isolation layer,
the first isolation layer includes a main portion disposed within the first recess and an extension portion attached to the main portion and disposed on the surface of the substrate, and a dielectric layer surrounds the extension portion of the first isolation layer.

12. The semiconductor structure of claim 11 , wherein a depth of the first inductor device or a depth of the second inductor device is between 10 and 20 μm.

13. The semiconductor structure of claim 11 , wherein a portion of the first isolation layer is exposed by the first magnetic layer.

14. The semiconductor structure of claim 11 , wherein the first isolation layer of the first inductor device is spaced apart from the third isolation layer of the second inductor device.

15. The semiconductor structure of claim 11 , wherein the dielectric layer is disposed over the first recess and the second recess.

16. A semiconductor structure, comprising:
a substrate including a surface; and
an inductor device extending into the substrate from the surface of the substrate and including a first isolation layer, a first magnetic layer over the first isolation layer, a second isolation layer over the first magnetic layer, and a conductive element surrounded by the second isolation layer, and a third isolation layer disposed over the second isolation layer and the conductive element, and a second magnetic layer disposed over the third isolation layer,
wherein at least a portion of the first isolation layer and at least a portion of the first magnetic layer are disposed within the substrate, the first isolation layer and the first magnetic layer form a step structure over the surface of the substrate, and a portion of the third isolation layer is exposed by the second magnetic layer.

17. The semiconductor structure of claim 16 , wherein the first isolation layer is conformal to a portion of the surface of the substrate.

18. The semiconductor structure of claim 16 , wherein the first isolation layer includes a main portion extending into the substrate and an extension portion attached to the main portion, disposed on the surface of the substrate and at least partially exposed by the first magnetic layer.

19. The method of claim 16 , wherein the third isolation layer is in contact with the conductive element, the second isolation layer and the first magnetic layer.

20. The method of claim 16 , wherein the first isolation layer, the first magnetic layer, the third isolation layer, and the second magnetic layer form the step structure over the substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Wei-Yu
• Chen Yang-Che
• Yang Yi-Lun

Classifications

• H10D1/20 Primary

  Inductors · CPC title