Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12426248-B2
Application number	US-202418420138-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Feb 22, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A method of manufacturing a semiconductor device including partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate, forming a gate structure in the recess, the gate structure including a first conductive pattern, a second conductive pattern on the first conductive pattern, and a gate mask on the second conductive pattern, partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the opening being lower than a lower surface of the exposed portion of the first conductive pattern, and forming a contact plug in the opening.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate;
forming a gate structure in the recess, the gate structure including:
a first conductive pattern;
a second conductive pattern on the first conductive pattern; and
a gate mask on the second conductive pattern;

partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the opening being lower than a lower surface of the exposed portion of the first conductive pattern; and
forming a contact plug in the opening.

2. The method according to claim 1 , wherein the first conductive pattern includes at least one of a metal or a metal nitride, and the second conductive pattern includes polysilicon.

3. The method according to claim 1 , the method further comprising:
partially etching the upper portion of the substrate to form an active pattern in the substrate; and
forming an isolation pattern covering at least a portion of a sidewall of the active pattern,
wherein partially etching the upper portion of the substrate to form the recess includes partially etching upper portions of the active pattern and the isolation pattern.

4. The method according to claim 3 , wherein partially etching the end portion of the gate structure in the first direction to form the opening includes partially etching a portion of the isolation pattern adjacent to the gate structure in the first direction.

5. The method according to claim 1 , wherein the opening includes:
a first portion extending through the end portions of the gate mask and the second conductive pattern of the gate structure; and
a second portion under the first portion, the second portion exposing the portion of the first conductive pattern, and
wherein a first angle of a sidewall of the first portion with respect to the upper surface of the substrate is greater than a second angle of a sidewall of the second portion with respect to the upper surface of the substrate.

6. The method according to claim 5 , wherein the second angle is greater than or equal to about 30 degrees and is less than about 70 degrees.

7. The method according to claim 5 , wherein the first angle is greater than or equal to about 70 degrees and equal to or less than about 90 degrees.

8. The method according to claim 5 , wherein the opening further includes a protrusion portion under the second portion, the protrusion portion being lower than the lower surface of the exposed portion of the first conductive pattern.

9. The method according to claim 8 , wherein a maximum width of the protrusion portion of the opening is equal to a minimum width of the second portion of the opening.

10. The method according to claim 8 , wherein the protrusion portion of the opening does not overlap the gate structure in a vertical direction perpendicular to the upper surface of the substrate.

11. The method according to claim 1 , wherein the gate structure further includes:
a barrier pattern covering a sidewall and a lower surface of the first conductive pattern; and
a gate insulation pattern covering a sidewall and a lower surface of the barrier pattern, and
wherein the opening exposes portions of the barrier pattern and the gate insulation pattern.

12. A method of manufacturing a semiconductor device, the method comprising:
partially etching an upper portion of a substrate to form a recess extending in a first direction parallel to an upper surface of the substrate;
forming a gate structure in the recess, the gate structure including:
a first conductive pattern;
a second conductive pattern on the first conductive pattern; and
a gate mask on the second conductive pattern;

partially etching an end portion of the gate structure in the first direction to form an opening, the opening including:
a first portion extending through end portions of the gate mask and the second conductive pattern of the gate structure, a sidewall of the first portion having a first angle with respect to the upper surface of the substrate;
a second portion under the first portion, the second portion exposing a portion of the first conductive pattern, a sidewall of the second portion having a second angle with respect to the upper surface of the substrate, and the first angle being greater than the second angle; and
a protrusion portion under the second portion, the protrusion portion being lower than a lower surface of the exposed portion of the first conductive pattern; and

forming a contact plug in the opening.

13. The method according to claim 12 , wherein the first conductive pattern includes at least one of a metal or a metal nitride, and the second conductive pattern includes polysilicon.

14. The method according to claim 12 , the method further comprising:
partially etching the upper portion of the substrate to form an active pattern in the substrate; and
forming an isolation pattern covering at least a portion of a sidewall of the active pattern,
wherein partially etching the upper portion of the substrate to form the recess includes partially etching upper portions of the active pattern and the isolation pattern.

15. The method according to claim 14 , wherein partially etching the end portion of the gate structure in the first direction to form the opening includes partially etching a portion of the isolation pattern adjacent to the gate structure in the first direction.

16. The method according to claim 12 , wherein the protrusion portion of the opening does not overlap the gate structure in a vertical direction perpendicular to the upper surface of the substrate.

17. The method according to claim 12 , wherein the gate structure further includes:
a barrier pattern covering a sidewall and a lower surface of the first conductive pattern; and
a gate insulation pattern covering a sidewall and a lower surface of the barrier pattern, and
wherein the opening exposes portions of the barrier pattern and the gate insulation pattern.

18. A method of manufacturing a semiconductor device, the method comprising:
partially etching an upper portion of a substrate to form an active pattern in the substrate;
forming an isolation pattern covering at least a portion of a sidewall of the active pattern;
partially etching upper portions of the active pattern and the isolation pattern to form a recess extending in a first direction parallel to an upper surface of the substrate;
forming a gate structure in the recess, the gate structure including:
a first conductive pattern;
a second conductive pattern on the first conductive pattern; and
a gate mask on the second conductive pattern;

forming a bit line structure intersecting, in a planar view, a middle portion of the active pattern and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction;
forming a first contact plug structure contacting each of opposing side end portions of the active pattern;
partially etching an end portion of the gate structure in the first direction to form an opening, the opening extending through end portions of the gate mask and the second conductive pattern of the gate structure to expose a portion of the first conductive pattern, and a bottom of the open

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Sohyeon
• Lee Wonchul
• Kim Jaehyun
• Jang Jaehyuk
• Choi Hyebin

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title