Method of manufacturing printed circuit board

Patent metadata

Field	Value
Publication number	US-12426165-B2
Application number	US-202418661939-A
Country	US
Kind code	B2
Filing date	May 13, 2024
Priority date	May 26, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A method of manufacturing a printed circuit board includes: forming a resist layer; exposing first areas of the resist layer spaced apart from each other; after exposing the first areas, exposing second areas of the resist layer, the second areas being spaces between the first areas; forming first and second openings spaced apart from each other in the first and second areas by developing the resist layer; and forming a plurality of conductor patterns by filling the first and second openings with conductors.

First claim

What is claimed is:

1. A method of manufacturing a printed circuit board, the method comprising:
forming a first resist layer;
forming first openings spaced apart from each other in the first resist layer;
forming first plating patterns spaced apart from each other by at least partially filling the first openings;
removing the first resist layer;
forming a second resist layer covering the first plating patterns;
forming second openings spaced apart from each other in the second resist layer; and
forming second plating patterns by at least partially filling the second openings,
wherein at least one of the second openings is formed in a space between adjacent ones of the first plating patterns to be spaced apart from the first plating patterns, and
at least another one of the second openings exposes only a portion of a top surface of at least one of the first plating patterns.

2. The method of claim 1 , wherein the forming of the second plating patterns by filling the second openings includes forming a via on the first plating pattern exposed through the at least another one of the second openings.

3. The method of claim 2 , further comprising:
forming a seed layer before the forming of the first resist layer; and
removing the second resist layer and partially removing the seed layer after the forming of the second plating patterns by filling the second openings.

4. The method of claim 3 , further comprising, after the partially removing of the seed layer:
forming an insulating layer covering the first plating patterns, the second plating patterns, and the via;
at least partially removing the insulating layer to expose the via; and
forming an upper conductor pattern layer on the insulating layer.

5. The method of claim 2 , further comprising:
forming a first seed layer before the forming of the first resist layer;
between the removing of the first resist layer and the forming of the second resist layer, partially removing the first seed layer; and
between the forming of the second openings and the forming of the second plating patterns by filling the second openings, forming a second seed layer at least partially on a surface of the second resist layer including inner surfaces of the second openings.

6. The method of claim 5 , wherein the second resist layer is a permanent resist.

7. The method of claim 1 , wherein the first plating patterns and/or the second plating patterns are formed by performing plating to be thicker than the first resist layer and/or the second resist layer, and then removing partial portions thereof protruding beyond the first resist layer and/or the second resist layer.

8. The method of claim 7 , wherein the first resist layer is formed on a seed layer.

9. The method of claim 1 , further comprising:
removing the second resist layer;
forming a third resist layer covering the first and second plating patterns; and
forming a third plating pattern spaced apart from each of the first and second plating patterns in the third resist layer,
wherein the third plating pattern is higher than each of the first and second plating patterns.

10. The method of claim 9 , further comprising forming a seed layer before the forming of the first resist layer, and
the first, second, and third plating layers are formed directly on the seed layer.

11. The method of claim 10 , further comprising, after the forming of the third plating pattern:
removing the third resist layer;
partially removing the seed layer;
forming an insulating layer covering the first to third plating patterns; and
forming an upper conductor pattern layer connected to the third plating pattern on the insulating layer.

12. The method of claim 9 , wherein the first plating patterns and the second plating patterns are alternately formed on a base.

13. A method of manufacturing a printed circuit board, the method comprising:
forming a first resist layer;
forming first openings spaced apart from each other in the first resist layer;
forming first plating patterns spaced apart from each other by at least partially filling the first openings;
removing the first resist layer;
forming a second resist layer covering the first plating patterns;
forming second openings spaced apart from each other in the second resist layer; and
forming second plating patterns by at least partially filling the second openings;
removing the second resist layer;
forming a third resist layer covering the first and second plating patterns and filing at least a portion between the first and second plating patterns to contact side surfaces of the first and second plating patterns;
forming a third opening spaced apart from the first plating patterns and the second plating patterns in the third resist layer; and
forming a third plating pattern by at least partially filling the third opening,
wherein the third plating pattern has a thickness greater than each of the first and second plating patterns.

14. The method of claim 13 , further comprising forming a seed layer before the forming of the first resist layer, and
the first, second, and third plating layers are formed directly on the seed layer.

15. The method of claim 14 , further comprising, after the forming of the third plating pattern:
removing the third resist layer;
partially removing the seed layer;
forming an insulating layer covering the first to third plating patterns; and
forming an upper conductor pattern layer connected to the third plating pattern on the insulating layer.

16. The method of claim 13 , wherein the first plating patterns and the second plating patterns are alternately formed on a base.

Assignees

• Samsung Electro Mech

Inventors

• Park Chan Jin
• Park Jong Eun
• Yang Hyun Seok
• Cho Sangik
• Okada Hiroki
• Cho Young Ook
• Jeon Mi Jeong
• Chung In Jae

Classifications

• C25D5/022

  using masking means · CPC title

• G03F7/20

  Exposure; Apparatus therefor (photographic printing apparatus for making copies G03B27/00) · CPC title

• H05K2203/025

  Abrading, e.g. grinding or sand blasting · CPC title

• C25D7/00

  Electroplating characterised by the article coated · CPC title

• H05K2203/1476

  Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning · CPC title