Systems and methods for utilizing photonic degrees of freedom in a photonic processor

Patent metadata

Field	Value
Publication number	US-12425119-B2
Application number	US-202318321384-A
Country	US
Kind code	B2
Filing date	May 22, 2023
Priority date	Jul 24, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Systems and methods for increasing throughput of a photonic processor by using photonic degrees of freedom (DOF) are provided. The photonic processor includes a multiplexer configured to multiplex, using at least one photonic DOF, multiple encoded optical signals into a multiplexed optical signal. The photonic processor also includes a detector coupled to an output of an optical path including the multiplexer, the detector being configured to generate a first current based on the multiplexed optical signal or a demultiplexed portion of the multiplexed optical signal. The photonic processor further includes a modulator coupled to and output of the detector, the modulator being configured to generate a second current by modulating the first current.

First claim

The invention claimed is:

1. A photonic processor configured to perform multiplication between a first matrix and a second matrix, the photonic processor comprising:
a multiplexer configured to generate a multiplexed optical signal by multiplexing, using at least one photonic degree of freedom, a first optical signal generated by a local oscillator and second optical signals generated by encoding numeric values of elements of the first matrix into optical signals received from one or more light sources; and
a modulator coupled to an output of the multiplexer and configured to generate an output signal by modulating a received signal originating from the multiplexer based on a numeric value of an element of the second matrix, wherein the output signal is representative of products of a numeric value of an encoded element of the first matrix and the numeric value of the element of the second matrix.

2. The photonic processor of claim 1 , further comprising a detector coupled between an output of the multiplexer and an input of the modulator wherein the detector is configured to generate a first current based on the multiplexed optical signal.

3. The photonic processor of claim 2 , wherein the received signal comprises the first current generated by the detector and the output signal comprises a second current generated by the modulator.

4. The photonic processor of claim 2 , wherein:
the detector comprises a plurality of detectors, each detector of the plurality of detectors being coupled to outputs of an optical path including the multiplexer and configured to generate the first current,
the modulator comprises a plurality of modulators, each modulator of the plurality of modulators being coupled to an output of one or more detectors of the plurality of detectors, and
the plurality of modulators are configured to generate second currents by modulating the first current based on numeric values of elements of the second matrix.

5. The photonic processor of claim 4 , further comprising a demultiplexer coupled to a combined output of the plurality of modulators, the demultiplexer configured to demultiplex the combined output of the plurality of modulators using demultiplexing signal having a frequency related to a frequency of the local oscillator.

6. The photonic processor of claim 1 , wherein the at least one photonic degree of freedom is one of a selection of wavelength or frequency.

7. The photonic processor of claim 3 , further comprising one or more differential optical encoders optically coupled to one or more inputs of the multiplexer, the one or more differential optical encoders being configured to generate the second optical signals by encoding numeric values of elements of the first matrix into the optical signals received from one or more light sources.

8. The photonic processor of claim 7 , wherein:
the second optical signals comprising top rail second optical signals and bottom rail second optical signals, and
the one or more differential optical encoders are configured to generate the top rail second optical signals and the bottom rail second optical signals by encoding the numeric values of elements of the first matrix into a difference between an absolute value of amplitudes of light in a top rail second optical signal and an absolute value of an amplitude of light in a bottom rail second optical signal.

9. The photonic processor of claim 8 , wherein:
the top rail second optical signals have a first frequency,
the bottom rail second optical signals have a second frequency, and
the first frequency and the second frequency are different than a frequency of the first optical signal generated by the local oscillator.

10. The photonic processor of claim 8 , wherein:
the multiplexed optical signal comprises a top rail multiplexed optical signal and a bottom rail multiplexed optical signal,
the multiplexer comprises a top rail multiplexer and a bottom rail multiplexer,
the top rail multiplexer is configured to generate the top rail multiplexed optical signal by multiplexing the top rail second optical signals, and
the bottom rail multiplexer is configured to generate the bottom rail multiplexed optical signal by multiplexing the bottom rail second optical signals.

11. The photonic processor of claim 10 , wherein:
the detector comprises a top rail detector coupled to an output of the top rail multiplexer and a bottom rail detector coupled to an output of the bottom rail multiplexer,
the first current comprises a top rail first current and a bottom rail first current,
the top rail detector is configured to generate the top rail first current using the top rail multiplexed optical signal, and
the bottom rail detector is configured to generate the bottom rail first current using the bottom rail multiplexed optical signal.

12. The photonic processor of claim 11 wherein:
the modulator is coupled to an output of the top rail detector and to an output of the bottom rail detector, and
the second current comprises a top rail second current and a bottom rail second current.

13. The photonic processor of claim 12 , wherein:
the detector comprises a first plurality of detectors and a second plurality of detectors,
the first plurality of detectors are coupled to outputs of an optical path including the top rail multiplexer,
the second plurality of detectors are coupled to outputs of an optical path including the bottom rail multiplexer, and
the first current comprises a top rail first current generated by the first plurality of detectors and a bottom rail first current generated by the second plurality of detectors.

14. The photonic processor of claim 13 , wherein:
the modulator comprises a plurality of modulators, each modulator of the plurality of modulators being coupled to an output of one of the first plurality of detectors and an output of one of the second plurality of detectors,
modulators of the plurality of modulators are configured to generate top rail second currents by modulating the top rail first current based on elements of the second matrix, and
the modulators of the plurality of modulators are configured to generate bottom rail second currents by modulating the bottom rail first current based on the elements of the second matrix.

15. The photonic processor of claim 14 , further comprising a demultiplexer coupled to a top rail output of the plurality of modulators and to a bottom rail output of the plurality of modulators, wherein:
the top rail output comprises a combined output of the top rail second currents,
the bottom rail output comprises a combined output of the bottom rail second currents, and
the demultiplexer is configured to demultiplex the top rail output and the bottom rail output to generate demultiplexed combined outputs comprising electrical signals.

16. The photonic processor of claim 15 , wherein the demultiplexer is configured to demultiplex the top rail output and the bottom rail output using intermediate frequency mixing.

17. The photonic processor of claim 16 , wherein the demultiplexer is configured to demultiplex the top rail output and the bottom rail output by mixing each of the top rail output and the bottom rail output with a pure tone at a frequency equal to a difference between a frequency of one of the optical signals received from one or more light sources and a frequency of the first optical signal generated by the local oscillator.

18. The photonic processor of claim 15 , further comprising summing circuitry configured to sum the electrical signals output by the demultiplex

Assignees

• Lightmatter Inc

Inventors

• Bunandar Darius
• Gould Michael
• Harris Nicholas C
• Ramey Carl

Classifications

• H04J14/0279

  WDM point-to-point architectures · CPC title

• H04B10/801

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title

• H04B10/5051 Primary

  using a series, i.e. cascade, combination of modulators · CPC title

• H04J14/0307 Primary

  Multiplexers; Demultiplexers · CPC title

• G06N7/01

  Probabilistic graphical models, e.g. probabilistic networks · CPC title