Manufacturing method of semiconductor structure and semiconductor structure thereof

Patent metadata

Field	Value
Publication number	US-12424499-B2
Application number	US-202217731145-A
Country	US
Kind code	B2
Filing date	Apr 27, 2022
Priority date	Apr 27, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor structure, comprising:
forming a conductive coil in an interconnection structure;
forming a first passivation layer over the interconnection structure;
forming a conductive layer over the first passivation layer;
reducing a thickness of a portion of the conductive layer;
patterning the conductive layer, thereby forming a conductive material disposed between a first conductive pad and a second conductive pad, wherein a thickness of the conductive material is substantially less than a thickness of the first conductive pad or a thickness of the second conductive pad;
forming an oxide layer over the first conductive pad, the second conductive pad and the conductive material;
measuring an induced current in the conductive coil through the first conductive pad and the second conductive pad; and
forming a stress buffering layer over the oxide layer, the first conductive pad, and the second conductive pad after the measuring of the induced current.

2. The manufacturing method of claim 1 , further comprising:
forming a first mask layer over the conductive layer, wherein the first mask layer leaves the portion of the conductive layer exposed; and
performing a dry etching operation to reduce the thickness of the portion of the conductive layer.

3. The manufacturing method of claim 2 , further comprising:
forming a second mask layer over the conductive layer, wherein the second mask layer covers the portion of the conductive layer.

4. The manufacturing method of claim 1 , further comprising:
forming a second passivation layer, wherein top surfaces of the first conductive pad, the second conductive pad, and the conductive material are exposed prior to the formation of the oxide layer.

5. The method of claim 1 , wherein the interconnection structure comprises a first conductive line and a second conductive line, wherein the first conductive line, the second conductive line and the conductive coil are in a same level.

6. The method of claim 5 , wherein the conductive coil is formed prior to or after a formation of the first conductive line and the second conductive line.

7. The method of claim 5 , wherein the conductive coil is formed concurrently with a formation of the first conductive line and the second conductive line.

8. A method for manufacturing a semiconductor structure, comprising receiving an interconnection structure comprising a conductive coil formed therein;
forming a passivation layer over the interconnection structure;
forming a conductive material over the passivation layer, wherein the conductive material overlaps the conductive coil;
forming a first conductive pad and a second conductive pad over the passivation layer, wherein the first conductive pad comprises a first pad portion over the passivation layer and a first via portion penetrating the passivation layer, the second conductive pad comprises a second pad portion over the passivation layer and a second via portion penetrating the passivation layer, and a thickness of the first pad portion and a thickness of the second pad portion are greater than a thickness of the conductive material;
measuring an induced current in the conductive coil through the first conductive pad and the second conductive pad; and
forming a stress buffering layer over the oxide layer after the measuring of the induced current, wherein the first conductive pad and the second conductive pad are electrically connected to the conductive coil.

9. The method of claim 8 , wherein the conductive material is separated from the first conductive pad and the second conductive pad.

10. The method of claim 8 , wherein the forming of the conductive material further comprises:
forming a conductive layer over the passivation layer;
forming a mask layer over the conductive layer, wherein the mask layer exposes a first portion of the conductive layer and covers second portions of the conductive layer;
etching the first portion of the conductive layer such that a thickness of the first portion of is less than a thickness of each second portion.

11. The method of claim 8 , wherein the forming of the first conductive pad and the second conductive pad further comprises:
forming a first opening and a second opening separated from each other in the passivation layer;
forming a conductive layer over the passivation layer, wherein the first opening and the second opening are filled with the conductive layer;
forming a mask layer over portions of the conductive layer; and
etching the conductive layer through the mask layer to form the first conductive pad and the second conductive pad.

12. The method of claim 11 , further comprising forming the first via portion in the first opening and the second via portion in the second opening.

13. The method of claim 8 , wherein the first conductive pad is electrically connected to the conductive coil through the first via portion, and the second conductive pad is electrically connected to the conductive coil through the second via portion.

14. The method of claim 11 , wherein the mask layer further covers the conductive material.

15. The method of claim 8 , wherein the forming of the conductive material is prior to the forming of the first conductive pad and the second conductive pad.

16. A method for manufacturing a semiconductor structure, comprising receiving an interconnection structure, wherein the interconnection structure comprises a conductive coil, a first conductive line and a second conductive line;
forming a first passivation layer over the interconnection structure;
forming a conductive material over the first passivation layer, wherein the conductive material overlaps the conductive coil;
forming a first conductive pad coupled to the first conductive line and a second conductive pad coupled to the second conductive line over the passivation layer, wherein the first conductive pad and the second conductive pad are separated from the conductive material;
forming a second passivation layer over the conductive material, the first conductive pad and the second conductive pad; and
patterning the second passivation layer to form openings exposing the conductive material, the first conductive pad and the second conductive pad, wherein the first conductive pad comprises a pad portion over the first passivation layer and a via portion penetrating the first passivation layer, and a thickness of the pad portion of the first conductive pad is different from than a thickness of the conductive material, wherein the forming of the conductive material and the forming of the first conductive pad and the second conductive pad further comprises:
forming a conductive layer over the first passivation layer;
performing a first etching to remove a first portion of the conductive layer to form a recess in the conductive layer; and
performing a second etching to remove second portions of the conductive layer to form the conductive material over the conductive coil, and to form the first conductive pad and the second conductive pad.

17. The method of claim 16 , wherein the thickness of the conductive material is less than a thickness of the first conductive pad and a thickness of the second conductive pad.

18. The method of claim 16 , wherein the first conductive line is electrically connected to the conductive coil through metal vias and a third conductive line under the conductive coil.

19. The method of claim 16 , wherein the second conductive line is in contact with the conductive coil.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ma Pei-Lum
• Jhong Kun Da
• Lu Hsueh-Han
• Chen Kun-Ei
• Chiang Chen-Chieh
• Wang Ling-Sung

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01951

  Changing the shapes of bond pads · CPC title

• H10W72/967

  Multiple bond pads having different functions · CPC title