Process method for improving reliability of metal gate high-voltage device

Patent metadata

Field	Value
Publication number	US-12424436-B2
Application number	US-202318173981-A
Country	US
Kind code	B2
Filing date	Feb 24, 2023
Priority date	Feb 28, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

The present application provides a process method for improving reliability of a metal gate high-voltage device. Stacks layers formed over the gate oxide layer and spaced apart from each other. An SiCN layer is deposited to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers. An HARP layer is deposited to covert the SiCN layer. The HARP layer over the stack layers and the slot regions is covered with a photoresist. Photolithography and etching are sequentially performed to open the HARP layer over the stack layers. The photoresist in the slot regions is reserved. The HARP layer over the stack layers outside the slot regions is removed. The operations are repeated for many times until the slot regions are filled with the HARP layer.

First claim

What is claimed is:

1. A process method for improving reliability of a metal gate high-voltage device, wherein the process method for improving the reliability of the metal gate high-voltage device at least comprises:
step 1: providing a semiconductor structure, the semiconductor structure comprising a high-voltage device active area; a gate oxide layer formed over the high-voltage device active area;
and stack layers formed over the gate oxide layer and spaced apart from each other, regions between the stack layers being slot regions;
step 2: depositing an SiCN layer to cover tops and sidewalls of the stack layers, and cover bottoms of slots between the stack layers;
step 3: depositing a high aspect ratio process (HARP) layer to cover the SiCN layer;
step 4: covering the HARP layer over the stack layers and the slot regions with a photoresist, sequentially performing photolithography and etching to open the HARP layer over the stack layers, and reserving the photoresist in the slot regions;
step 5: removing the HARP layer over the stack layers outside the slot regions;
step 6: repeating steps 3 to step 5 for many times until the slot regions are filled with the HARP layer; and
step 7: performing etching to remove the SiCN layer over the stack layers.

2. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 1, the stack layers are formed by sequentially stacking at least polysilicon, silicon nitride, and a plasma enhanced oxide (PEOX) layer from bottom to top.

3. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 2, a thickness of the SiCN layer is 90 Å.

4. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 2, a method for depositing the SiCN layer is chemical vapor deposition.

5. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 3, a thickness of the deposited HARP layer is 150 Å.

6. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 5, a wet etching process is adopted to remove the HARP layer over the stack layers outside the slot regions.

7. The process method for improving the reliability of the metal gate high-voltage device according to claim 6 , wherein in step 5, etching solution in the wet etching process is hydrofluoric acid.

8. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 5, a concentration of hydrofluoric acid is 300:1 or 200:1.

9. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 6, step 3 to step 5 are repeated for 1-2 times.

10. The process method for improving the reliability of the metal gate high-voltage device according to claim 1 , wherein in step 7, a method for performing etching to remove the SiCN layer is dry etching.

Assignees

• Shanghai Huali Integrated Circuit Corp

Inventors

• Zhan yaoyu
• Wang Qiwei
• Zhang Zhigang

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6334

  using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title

• H10P14/6905 Primary

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10D64/01334

  by defining the insulator using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title

• H10D64/01304 Primary

  characterised by the conductor · CPC title