One-time programmable (ROTP) NVM

Patent metadata

Field	Value
Publication number	US-12424294-B2
Application number	US-202217937012-A
Country	US
Kind code	B2
Filing date	Sep 30, 2022
Priority date	Jun 6, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

First claim

What is claimed is:

1. A method comprising:
receiving a first program bit address, the first program bit address associated with a first plurality of redundant bit addresses, wherein the first program bit address is associated with a first transistor-based memory cell, and wherein the first plurality of redundant bit addresses are each associated with a respective transistor-based memory cell;
providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell;
reading a first bit value from the first transistor-based memory cell via a first bit line;
reading redundant bit values from transistor-based memory cells associated with the first plurality of redundant bit addresses via respective bit lines;
when one of the first bit value and the redundant bit values does not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values read from the transistor-based memory cells associated with the first plurality of redundant bit addresses; and
when the majority bit value does not match the first write value, asserting a flag signal indicative of a failed programing of the first program bit address to the first write value.

2. The method of claim 1 , wherein providing the programing pulse to the first word line comprises providing a first positive voltage to the first word line, wherein the first word line is incapable of receiving a negative voltage.

3. The method of claim 1 , wherein each of the transistor-based memory cells associated with the first plurality of redundant bit addresses is coupled to a respective word line, the method further comprising, when one of the first bit value and the redundant bit values does not match the first write value, providing an additional programing pulse to the word line associated with the one of the first bit value and the redundant bit values, and wherein determining the majority bit value comprises determining the majority bit value after providing the additional programing pulse.

4. The method of claim 1 , wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array, the method further comprising testing the OTP memory array by programing a first row and a first column of the OTP memory array to the first write value.

5. The method of claim 4 , further comprising preventing a read operation on the first row and first column of the OTP memory array.

6. The method of claim 1 , wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising reading a second bit value from a transistor-based memory cell of the non-OTP memory array sector by comparing a current from an associated bit line of the non-OTP memory array sector with an adaptive current threshold, wherein reading the first bit value from the first transistor-based memory cell via the first bit line comprises comparing a current from the first bit line with a fixed current threshold.

7. The method of claim 1 , wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising programing a second bit value to a second transistor-based memory cell of the non-OTP memory array sector by providing a first programing voltage to a second word line associated with the second transistor-based memory cell, wherein providing the programing pulse to the first word line comprises providing a second programing voltage that is higher than the first programing voltage.

8. The method of claim 1 , wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising reading a second bit value from a second transistor-based memory cell of the non-OTP memory array sector by providing a first read voltage to a second word line associated with the second transistor-based memory cell, wherein reading the first bit value from the first transistor-based memory cell comprises providing a second read voltage to the first transistor-based memory cell that is higher than the first read voltage.

9. The method of claim 1 , wherein each of the transistor-based memory cells associated with the first program bit address and the first plurality of redundant bit addresses is a multi-bit memory cell.

10. The method of claim 1 , further comprising:
receiving a plurality of additional program bit addresses, wherein each of the plurality of additional program bit addresses is associated with a respective multi-bit transistor-based memory cell; and
programing each of the multi-bit transistor-based memory cells associated with the plurality of additional program bit addresses to the first write value, wherein, after programing each of the multi-bit transistor-based memory cells, each bit of each of the multi-bit transistor-based memory cells is programed to the first write value.

11. The method of claim 1 , wherein the first write value corresponds to a logic 0.

12. The method of claim 1 , wherein the first transistor-based memory cell and the transistor-based memory cells associated with the first plurality of redundant bit addresses are part of a one-time programmable (OTP) memory array sector of a memory, the memory further comprising a non-OTP memory array sector, the method further comprising:
receiving a memory address;
when the memory address corresponds to a memory cell of the non-OTP memory array sector, setting an output of a negative voltage generator to a target negative voltage; and
when the memory address corresponds to a memory cell of the OTP memory array sector, setting the output of the negative voltage generator to a no-erase voltage that is different from the target negative voltage.

13. The method of claim 12 , wherein the no-erase voltage is equal to 0 V.

14. A circuit comprising:
a plurality of transistor-based memory cells arranged in rows and columns, each transistor-based memory cell comprising first and second bit line terminals coupled to associated bit lines of a plurality of bit lines, and a gate terminal coupled to an associated word line of a plurality of word lines, wherein each word line of the plurality of word lines is coupled to the gate terminals of the transistor-based memory cells of an associated row; and
a controller configured to:
cause a programing pulse to be provided to a first word line coupled to a first transistor-based memory cell of the plurality of transistor-based memory cells to write a first write value to the first transistor-based memory cell,

cause a first bit value to be read from the first transistor-based memory cell via a first bit line of the plurality of bit lines,
cause redundant bit values to be read from redundant transistor-based memory cells of the plurality of transistor-based memory cells, wherein the redundant transistor-based memory cells are configured to store the same value as t

Assignees

• Infineon Technologies LLC

Inventors

• Yogev Yoav
• Givant Amichai
• Sofer Yair
• He Yi

Classifications

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C29/34

  Accessing multiple bits simultaneously · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title