Semiconductor memory apparatus and semiconductor integrated circuit apparatus

Patent metadata

Field	Value
Publication number	US-9293227-B1
Application number	US-201514797190-A
Country	US
Kind code	B1
Filing date	Jul 13, 2015
Priority date	Feb 16, 2015
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A memory control circuit 10 controls an operation of reading stored data from a memory cell 50 connected to a word line WL and a bit line BL based on an address Address including a row address Ax and a column address Ay. When the address Address includes redundancy addresses P 1 to P 4 designating a word line WLa or a bit line BLc connected to a specific memory cell Cc, redundancy decoders 13 - 1 to 13 - 4 replace the specific memory cell Cc with a redundancy memory cell RCc connected to redundancy word lines RWL 1 and RWL 2 or redundancy bit lines RBL 1 and RBL 2 . Redundancy address latch circuits 12 - 1 to 12 - 4 respectively hold the redundancy addresses P 1 to P 4 , and erase the held redundancy addresses P 1 to P 4 based on a reset signal RS inputted from the memory control circuit 10.

First claim

What is claimed is:

1. A semiconductor memory apparatus, comprising:
a plurality of memory cells, respectively connected to a plurality of word lines and bit lines intersecting each other, and storing data inputted from the bit lines;
a memory control circuit, based on an address comprising a row address designating each of the word lines and a column address designating each of the bit lines, controlling an operation of reading the stored data from the memory cell connected to the word line and the bit line designated by the row address and the column address;
a redundancy decoder, when the address comprises a redundancy address designating a word line or bit line connected to a specific memory cell, replacing the specific memory cell with a redundancy memory cell connected to a predetermined word line or bit line in the plurality of memory cells; and
a plurality of redundancy address latch circuits, respectively holding the redundancy addresses, and erasing the held redundancy addresses based on a reset signal inputted from the memory control circuit.

2. The semiconductor memory apparatus of claim 1 , wherein
each of the redundancy address latch circuits holds the redundancy address based on a separately inputted enable signal.

3. The semiconductor memory apparatus of claim 1 , further comprising:
a fuse circuit, comprising fuses for storing the redundancy address in a non-volatile manner; and
a switch circuit, selectively switching between the redundancy address held by the redundancy address latch circuit and the redundancy address stored in the fuse circuit, and outputting the same to the redundancy decoder, wherein
when the address comprises a redundancy address from the switch circuit, the redundancy decoder replaces the specific memory cell with the redundancy memory cell.

4. The semiconductor memory apparatus of claim 3 , further comprising:
a first priority control circuit, when the fuse circuit has the redundancy address stored therein, causing the switch circuit to preferentially select the redundancy address stored in the fuse circuit over the redundancy address held by the redundancy address latch circuit.

5. The semiconductor memory apparatus of claim 1 , wherein
the plurality of redundancy address latch circuits comprise:
at least one first redundancy address latch circuit, holding a redundancy row address designating the word line connected to the specific memory cell; and
at least one second redundancy address latch circuit, holding a redundancy column address designating the bit line connected to the specific memory cell,
and wherein the semiconductor memory apparatus further comprises:
a second priority control circuit, controlling to preferentially select either of the first redundancy address latch circuit and the second redundancy address latch circuit, so as to write the redundancy row address or the redundancy column address in the selected redundancy address latch circuit.

6. The semiconductor memory apparatus of claim 5 , further comprising:
a counter, counting a number of the first redundancy address latch circuit holding the redundancy row address and a number of the second redundancy address latch circuit holding the redundancy column address.

7. The semiconductor memory apparatus of claim 6 , further comprising:
a sensor, detecting a temperature or a supply voltage of the semiconductor memory apparatus,
wherein the second priority control circuit preferentially selects either of the first redundancy address latch circuit and the second redundancy address latch circuit depending on the temperature or the supply voltage detected by the sensor.

8. The semiconductor memory apparatus of claim 1 , wherein
each of the redundancy address latch circuits comprises a volatile storage circuit.

9. A semiconductor integrated circuit apparatus, comprising the semiconductor memory apparatus of claim 1 .

Assignees

• Powerchip Technology Corp

Inventors

• Takasugi Atsushi

Classifications

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C29/78

  using programmable devices · CPC title

• G11C29/82

  for EEPROMs · CPC title

• G11C16/04

  using variable threshold transistors, e.g. FAMOS · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title