Three-dimensional memory device containing structurally reinforced pedestal channel portions and methods of making the same
US-10256252-B1 · Apr 9, 2019 · US
US12424282B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12424282-B2 |
| Application number | US-202217752207-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 24, 2022 |
| Priority date | May 24, 2022 |
| Publication date | Sep 23, 2025 |
| Grant date | Sep 23, 2025 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, re disclosed.
Opening claim text (preview).
The invention claimed is: 1. A method used in forming a memory array comprising strings of memory cells, comprising: forming a conductor tier comprising conductor material on a substrate; forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from material of the second tiers; forming conducting material in a lower of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising: forming conductively-doped semiconductive material in the lower first tier against the channel material of the individual channel-material strings, the conductively-doped semiconductive material comprising an upper portion and a lower portion having a void-space vertically there-between; and forming intermediate material into the void-space, the intermediate material being of different composition from that of the conductively-doped semiconductive material and comprising at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. 2. The method of claim 1 wherein the at least one comprises carbon. 3. The method of claim 1 wherein the at least one comprises nitrogen. 4. The method of claim 1 wherein the at least one comprises the metal. 5. The method of claim 1 wherein the at least one comprises the n-type conductively-doped semiconductive material also comprising boron. 6. The method of claim 1 wherein the at least one comprises more than one of carbon, nitrogen, oxygen, the metal, and n-type conductively-doped semiconductive material also comprising boron. 7. The method of claim 1 wherein all of the at least one is present at 1×10 10 to 3×10 22 atoms/cm 3 . 8. The method of claim 7 wherein all of the at least one is present at at least 1×10 14 atoms/cm 3 . 9. The method of claim 8 wherein all of the at least one is present at 5×10 19 to 5×10 21 atoms/cm 3 . 10. The method of claim 1 wherein the conductively doped semiconductive material is not formed directly against the channel material. 11. The method of claim 1 wherein the conductively doped semiconductive material is formed directly against the channel material. 12. The method of claim 1 wherein the conductively doped semiconductive material has total concentration of all conductivity-modifying dopant therein of 0.01 atomic percent to 30 atomic percent. 13. The method of claim 12 wherein the total concentration is no greater than 1×10 23 atoms/cm 3 . 14. The method of claim 1 wherein the intermediate material is formed into the void-space directly against the conductively-doped semiconductive material. 15. The method of claim 1 wherein the intermediate material is formed into the void-space to fill such void-space. 16. The method of claim 1 wherein the lower first tier is the lowest of the first tiers. 17. The method of claim 1 wherein the intermediate material is thinner than each of the upper and lower portions of the conductively-doped semiconductive material. 18. The method of claim 1 wherein the intermediate material is conductive at least in a finished circuitry construction. 19. A method used in forming a memory array comprising strings of memory cells, comprising: forming a conductor tier comprising conductor material on a substrate; forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, channel-material strings extending through the first tiers and the second tiers, material of the first tiers being of different composition from material of the second tiers; forming conducting material in a lowest of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, the forming of the conducting material comprising: forming undoped semiconductive material in the lowest first tier directly against a sidewall of the channel material of the individual channel-material strings, the undoped semiconductive material comprising an upper portion and a lower portion having a void-space vertically there-between, the undoped semiconductive material having total concentration of all conductivity-modifying dopant therein of 0 atomic percent to less than 0.01 atomic percent; forming conductively-doped semiconductive material in the void-space directly against the undoped semiconductive material, the conductively-doped semiconductive material comprising an upper portion and a lower portion having a remaining portion of the void-space vertically there-between, the conductively-doped semiconductive material having total concentration of all conductivity-modifying dopant therein of 0.01 atomic percent to 30 atomic percent; and forming intermediate material into and to fill remaining volume of the remaining portion of the void-space and directly against the conductively-doped semiconductive material, the intermediate material being of different composition from that of the conductively-doped semiconductive material and comprising at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. 20. The method of claim 19 wherein the upper and lower portions of the undoped semiconductive material are each thinner than the intermediate material. 21. The method of claim 19 wherein the upper and lower portions of the undoped semiconductive material are each thinner than the upper and lower portions of the conductively-doped semiconductive material. 22. The method of claim 19 wherein the intermediate material is thinner than each of the upper and lower portions of the conductively-doped semiconductive material. 23. The method of claim 19 wherein the upper and lower portions of the undoped semiconductive material are each thinner than the intermediate material. 24. The method of claim 19 wherein each of the undoped semiconductive material, the conductively-doped semiconductive material, and the intermediate material comprises polysilicon. 25. The method of claim 19 wherein the at least one comprises carbon. 26. The method of claim 19 wherein the at least one comprises nitrogen. 27. The method of claim 19 wherein the at least one comprises the metal. 28. The method of claim 19 wherein the at least one comprises the n-type conductively-doped semiconductive material also comprising boron. 29. The method of claim 19 wherein all of the at least one is present at 1×10 10 to 3×10 22 atoms/cm 3 . 30. The method of claim 29 wherein all of the at least one is present at at least 1×10 14 atoms/cm 3 . 31. The method of claim 30 wherein all of the at least one is present at 5×10 19 to 5×10 21 atoms/cm 3 . 32. The method of claim 19 wherein the intermediate material is conductive at least in a finished circuitry construction.
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
characterised by the top-view layout · CPC title
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
characterised by the top-view layout · CPC title
comprising cells having several storage transistors connected in series · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.