Driving circuit, driving method, driving module and display device

Patent metadata

Field	Value
Publication number	US-12424176-B2
Application number	US-202318839667-A
Country	US
Kind code	B2
Filing date	Dec 18, 2023
Priority date	Dec 19, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A driving circuit includes a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; N is a positive integer; the first gating circuit controls to write the gating input signal into the first first node under the control of the gating control signal; the first output circuit controls to connect the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and controls to connect the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node; the first third control node and the first second control node are different nodes.

First claim

What is claimed is:

1. A driving circuit, comprising a first driving signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; wherein N is a positive integer;
the first driving signal generation circuit is electrically connected to a first first control node, a first second control node and an Nth stage of driving signal output terminal respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first first control node and a potential of the first second control node;
the first output control circuit is electrically connected to a first first node, the first first control node and a first second node respectively, and is configured to control to connect the first first control node and the first second node under the control of a potential of the first first node;
the first gating circuit is electrically connected to the first first node, a gating input terminal and a gating control terminal respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first first node under the control of a gating control signal provided by the gating control terminal;
the first first energy storage circuit is electrically connected to the first first node and the first second node respectively, and is configured to control a potential of the first second node according to the potential of the first first node;
the first second energy storage circuit is electrically connected to a first third control node and an Nth stage of output driving terminal respectively, and is configured to control a potential of the first third control node according to an Nth stage of driving output signal provided by the Nth stage of output driving terminal;
the first output circuit is electrically connected to the first second node, the first third control node, a first voltage terminal, a second voltage terminal and the Nth stage of output driving terminal respectively, and is configured to control the connection between the Nth stage of output driving terminal and the first voltage terminal under the control of the potential of the first second node, and control the connection between the Nth stage of output driving terminal and the second voltage terminal under the control of the potential of the first third control node;
the first third control node and the first second control node are different nodes.

2. The driving circuit according to claim 1 , wherein the first gating circuit is configured to control to write the gating input signal provided by the gating input terminal into the first first node when a potential of an (N-1)th stage of the first third node is a second voltage and a potential of an Nth stage of driving signal is the second voltage.

3. The driving circuit according to claim 1 , wherein the first gating circuit includes a first first transistor; a gate electrode of the first first transistor is electrically connected to the gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the gating input terminal.

4. The driving circuit according to claim 1 , wherein the gating control terminal includes a first gating control terminal and a second gating control terminal; the first gating circuit includes a first first transistor and a first second transistor;
a gate electrode of the first first transistor is electrically connected to the first gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to a first electrode of the first second transistor;
a gate electrode of the first second transistor is electrically connected to the second gating control terminal, and a second electrode of the first second transistor is electrically connected to the gating input terminal;
the first gating control terminal is the Nth stage of driving signal output terminal, the second gating control terminal is the (N-1)th stage of first third node, and the first first transistor and the first second transistor are both p-type transistors; or,
the first gating control terminal is the (N-1)th stage of first third node, the second gating control terminal is the Nth stage of driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors; or,
the first gating control terminal is the (N-1)th stage of driving signal output terminal, the second gating control terminal is the Nth stage of driving signal output terminal, the first first transistor is an n-type transistor, and the first second transistor is a p-type transistor; or,
the first gating control terminal is the Nth stage of driving signal output terminal, the second gating control terminal is the (N-1)th stage of driving signal output terminal, the first first transistor is a p-type transistor, and the first second transistor is an n-type transistor; or,
the first gating control terminal is connected to an inverted signal of the (N-1)th stage of driving signal, the second gating control terminal is the Nth stage of driving signal output terminal, and the first first transistor and the first second transistor are both p-type transistors; or,
the first gating control terminal is the Nth stage of driving signal output terminal, and the second gating control terminal is connected to the inverted signal of the (N-1)th stage of driving signal; the first first transistor and the first second transistor are both p-type transistors; or,
the first gating control terminal is the (N-1)th stage of driving signal terminal, the second gating control terminal is connected to an inverted signal of the Nth stage of driving signal, and the first first transistor and the first second transistor are both n-type transistors; or,
the first gating control terminal is connected to the inverted signal of the Nth stage of driving signal, the second gating control terminal is the (N-1)th stage of driving signal terminal, and the first first transistor and the first second transistor are both n-type transistors.

5. The driving circuit according to claim 1 , wherein the first first energy storage circuit includes a first first capacitor, and the first second energy storage circuit includes a first second capacitor;
a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node;
a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the Nth stage of output driving terminal;
or
wherein the first output control circuit includes a first third transistor;
a gate electrode of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node;
or
the driving circuit further includes a first second node control circuit; wherein
the first second node control circuit is electrically connected to the first third control node, the first second node and the first voltage terminal, respectively, and is configured to control the connection between the first second node and the first voltage terminal un

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yu Ziyang
• Qiu Haijun
• Hu Ming
• Jiang Zhiliang
• Wu Jianpeng
• Cheng Tianyi
• Zhao Erjin
• Chen Wenbo
• Ai Sifei
• Liu Cong
• Guo Yonglin

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title