Pixel circuit, pixel driving method and display device

Patent metadata

Field	Value
Publication number	US-12424173-B2
Application number	US-202318561164-A
Country	US
Kind code	B2
Filing date	Feb 27, 2023
Priority date	Feb 27, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

The present disclosure provides a pixel circuit, a pixel driving method and a display device. The pixel circuit includes a light-emitting element, a driving circuitry, a first energy storage circuitry, a second energy storage circuitry, a data writing circuitry and a compensation control circuitry. The data writing circuitry writes a data voltage into a second node under the control of a first scanning signal from a first scanning end. The compensation control circuitry controls a first node to be electrically coupled to a second end of the driving circuitry under the control of a second scanning signal from a second scanning end. An effective enabling time period of the second scanning end does not overlap with, and has a length greater than, an effective enabling time period of the first scanning end.

First claim

What is claimed is:

1. A pixel circuit, comprising a light-emitting element, a driving circuitry, a first energy storage circuitry, a second energy storage circuitry, a data writing circuitry and a compensation control circuitry, wherein a first end of the first energy storage circuitry is electrically coupled to a first node, a second end of the first energy storage circuitry is electrically coupled to a second node, and the first energy storage circuitry is configured to store electric energy;
a first end of the second energy storage circuitry is electrically coupled to the second node, a second end of the second energy storage circuitry is electrically coupled to a first voltage end, and the second energy storage circuitry is configured to store electric energy;
the data writing circuitry is electrically coupled to a first scanning end, a data line and the second node, and configured to write a data voltage from the data line into the second node under the control of a first scanning signal from the first scanning end;
the compensation control circuitry is electrically coupled to a second scanning end, the first node and a second end of the driving circuitry, and configured to control the first node to be electrically coupled to the second end of the driving circuitry under the control of a second scanning signal from the second scanning end;
a control end of the driving circuitry is electrically coupled to the first node, a first end of the driving circuitry is electrically coupled to a power source voltage end, the second end of the driving circuitry is electrically coupled to the light-emitting element, and the driving circuitry is configured to drive the light-emitting element under the control of a potential at the first node; and
an effective enabling time period of the second scanning end does not overlap with an effective enabling time period of the first scanning end, and a length of the effective enabling time period of the second scanning end is greater than a length of the effective enabling time period of the first scanning end;
wherein the pixel circuit further comprises a first light-emission control circuitry and a second light-emission control circuitry, wherein the first end of the driving circuitry is electrically coupled to the power source voltage end via the first light-emission control circuitry, the second end of the driving circuitry is electrically coupled to a first electrode of the light-emitting element via the second light-emission control circuitry, and a second electrode of the light-emitting element is electrically coupled to a second voltage end;
the first light-emission control circuitry is electrically coupled to a first light-emission control end, the power source voltage end and the first end of the driving circuitry, and configured to control the power source voltage end to be electrically coupled to the first end of the driving circuitry under the control of a first light-emission control signal from the first light-emission control end;
the second light-emission control circuitry is electrically coupled to a second light-emission control end, the second end of the driving circuitry and the first electrode of the light-emitting element, and configured to control the second end of the driving circuitry to be electrically coupled to the first electrode of the light-emitting element under the control of a second light-emission control signal from the second light-emission control end;
wherein the pixel circuit further comprises a first initialization circuitry and a second initialization circuitry, wherein the first initialization circuitry is electrically coupled to a first resetting control end, a first initial voltage end and the second end of the driving circuitry, and configured to write a first initial voltage from the first initial voltage end into the second end of the driving circuitry under the control of a first resetting control signal from the first resetting control end;
the second initialization circuitry is electrically coupled to a second resetting control end, a second initial voltage end and the first electrode of the light-emitting element, and configured to write a second initial voltage from the second initial voltage end into the first electrode of the light-emitting element under the control of a second resetting control signal from the second resetting control end; and
a length of an effective enabling time period of the first resetting control end is less than a length of the effective enabling time period of the second scanning end, and the effective enabling time period of the first resetting control end overlaps within the effective enabling time period of the second scanning end.

2. The pixel circuit according to claim 1 , wherein the effective enabling time period of the first resetting control end does not overlap with an effective enabling time period of the first light-emission control end.

3. The pixel circuit according to claim 1 , wherein the first initialization circuitry comprises a fifth transistor, and the second initialization circuitry comprises a sixth transistor;
a gate electrode of the fifth transistor is electrically coupled to the first resetting control end, a first electrode of the fifth transistor is electrically coupled to the first initial voltage end, and a second electrode of the fifth transistor is electrically coupled to the second end of the driving circuitry; and
a gate electrode of the sixth transistor is electrically coupled to the second resetting control end, a first electrode of the sixth transistor is electrically coupled to the second initial voltage end, and a second electrode of the sixth transistor is electrically coupled to the first electrode of the light-emitting element.

4. The pixel circuit according to claim 1 , further comprising a first resetting circuitry and a second resetting circuitry, wherein the first resetting circuitry is electrically coupled to a third scanning end, a first reference voltage end and the second node, and configured to write a first reference voltage from the first reference voltage end into the second node under the control of a third scanning signal from the third scanning end; and
the second resetting circuitry is electrically coupled to a third resetting control end, a second reference voltage end and the first end of the driving circuitry, and configured to write a second reference voltage from the second reference voltage end into the first end of the driving circuitry under the control of a third resetting control signal from the third resetting control end.

5. The pixel circuit according to claim 4 , wherein the first resetting circuitry comprises a seventh transistor, and the second resetting circuitry comprises an eighth transistor;
a gate electrode of the seventh transistor is electrically coupled to the third scanning end, a first electrode of the seventh transistor is electrically coupled to the first reference voltage end, and a second electrode of the seventh transistor is electrically coupled to the second node;
a gate electrode of the eighth transistor is electrically coupled to the third resetting control end, a first electrode of the eighth transistor is electrically coupled to the second reference voltage end, and a second electrode of the eighth transistor is electrically coupled to the first end of the driving circuitry; and
the seventh transistor is an oxide transistor or a low-temperature polysilicon transistor.

6. The pixel circuit according to claim 1 , further comprising a resetting circuitry electrically coupled to a resetting control end, a reference voltage end, the second node and the first end of the driving circuitry, and configured to write a reference voltage from the reference voltage end into the second node and/or the

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Huang Yao
• Liu Lang
• Wei Xinyu

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G3/3258

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title