Pixel of an organic light emitting diode display device, and organic light emitting diode display device

Patent metadata

Field	Value
Publication number	US-11508320-B2
Application number	US-202117471217-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 11, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A pixel of an OLED display device includes a first capacitor, a second capacitor, a first transistor configured to generate a driving current, a second transistor configured to transfer a data voltage to a first node, a third transistor configured to diode-connect the first transistor, a fourth transistor configured to transfer an initialization voltage to the second node, a fifth transistor configured to transfer a reference voltage to the first node, a sixth transistor configured to couple a drain of the first transistor and an anode of an organic light emitting diode, a seventh transistor configured to transfer the initialization voltage to the anode of the organic light emitting diode, an eighth transistor configured to transfer the initialization voltage to the drain of the first transistor, and the organic light emitting diode.

First claim

What is claimed is:

1. A pixel of an organic light emitting diode (OLED) display device, the pixel comprising:
a first capacitor coupled between a first power supply voltage line and a first node;
a second capacitor coupled between the first node and a second node;
a first transistor configured to generate a driving current based on a voltage of the second node;
a second transistor configured to transfer a data voltage to the first node in response to a first scan signal;
a third transistor configured to diode-connect the first transistor in response to a second scan signal;
a fourth transistor configured to transfer an initialization voltage to the second node in response to a third scan signal;
a fifth transistor configured to transfer a reference voltage to the first node in response to the second scan signal;
a sixth transistor configured to couple a drain of the first transistor and an anode of an organic light emitting diode in response to an emission signal;
a seventh transistor configured to transfer the initialization voltage to the anode of the organic light emitting diode in response to a fourth scan signal; and
an eighth transistor configured to transfer the initialization voltage to the drain of the first transistor in response to a fifth scan signal,
wherein the organic light emitting diode includes the anode and a cathode coupled to a second power supply voltage line,
wherein the eighth transistor is not turned on in a normal mode in which a display panel is driven at a fixed frame frequency, and
wherein the eighth transistor is turned on to initialize the drain of the first transistor in a variable frequency mode in which the display panel is driven at a variable frame frequency.

2. The pixel of claim 1 , wherein the eighth transistor includes a gate receiving the fifth scan signal, a source coupled to the drain of the first transistor, and a drain coupled to an initialization voltage line.

3. The pixel of claim 1 , wherein the seventh transistor is turned on to initialize the organic light emitting diode in the a normal mode, and
wherein the seventh transistor is not turned on in the a variable frequency mode.

4. The pixel of claim 1 , wherein each frame period in the normal mode includes a gate initialization period in which a gate of the first transistor is initialized, a threshold voltage compensation period in which a threshold voltage of the first transistor is compensated, a diode initialization period in which the organic light emitting diode is initialized, a data writing period in which the data voltage is applied to the first node, and an emission period in which the organic light emitting diode emits light, and
wherein each frame period in the a variable frequency mode includes the gate initialization period, the threshold voltage compensation period, a drain initialization period in which the drain of the first transistor is initialized, the data writing period, and the emission period.

5. The pixel of claim 4 , wherein, in the drain initialization period,
the emission signal has an off level,
the fifth scan signal has an on level,
the first, second, third and fourth scan signals have the off level, and
the eighth transistor is turned on to apply the initialization voltage to the drain of the first transistor.

6. The pixel of claim 4 , wherein a time length of the threshold voltage compensation period is longer than a time length of the data writing period.

7. The pixel of claim 4 , wherein the diode initialization period overlaps the gate initialization period or the threshold voltage compensation period.

8. The pixel of claim 4 , wherein the drain initialization period is located between the data writing period and the emission period.

9. The pixel of claim 1 , wherein the second, third, fourth and fifth transistors are dual transistors.

10. The pixel of claim 1 , wherein a first portion of the first through eighth transistors is implemented with a p-type metal oxide semiconductor (PMOS) transistor, and
wherein a second portion of the first through eighth transistors is implemented with an n-type metal oxide semiconductor (NMOS) transistor.

11. The pixel of claim 1 , wherein the initialization voltage transferred by the fourth transistor is a first initialization voltage, the initialization voltage transferred by the seventh transistor is a second initialization voltage and the initialization voltage transferred by the eighth transistor is a third initialization voltage which are different from each other and are transferred through different initialization voltage lines.

12. The pixel of claim 1 , wherein the initialization voltage transferred by the seventh transistor is a second initialization voltage and the initialization voltage transferred by the eighth transistor is a third initialization voltage which are different from each other and are transferred through different initialization voltage lines.

13. The pixel of claim 12 , wherein the initialization voltage transferred by the fourth transistor is a same voltage as the initialization voltage transferred by the seventh transistor or the initialization voltage transferred by the eighth transistor.

14. The pixel of claim 1 , wherein the initialization voltage transferred by the fourth transistor, the initialization voltage transferred by the seventh transistor and the initialization voltage transferred by the eighth transistor are different from each other and are transferred through different initialization voltage lines.

15. The pixel of claim 1 , wherein a signal line transferring the fourth scan signal and a signal line transferring the fifth scan signal are electrically connected to each other.

16. An organic light emitting diode (OLED) display device comprising:
a display panel including a plurality of pixels;
a data driver configured to provide a data voltage to each of the plurality of pixels;
a scan driver configured to provide a gate writing signal, a gate initialization signal and a gate drain signal to each of the plurality of pixels;
an emission driver configured to provide an emission signal to each of the plurality of pixels; and
a controller configured to control the data driver, the scan driver and the emission driver,
wherein each of the plurality of pixels includes:
a first capacitor coupled between a first power supply voltage line and a first node;
a second capacitor coupled between the first node and a second node;
a driving transistor configured to generate a driving current based on a voltage of the second node;
a switching transistor configured to transfer the data voltage to the first node in response to the gate writing signal;
a gate initialization transistor configured to transfer a gate initialization voltage to the second node in response to the gate initialization signal;
an emission transistor configured to couple a drain of the driving transistor and an anode of an organic light emitting diode in response to the emission signal; and
a drain initialization transistor configured to transfer a drain initialization voltage to the drain of the driving transistor in response to the gate drain signal, and
wherein the organic light emitting diode includes the anode and a cathode coupled to a second power supply voltage line,
wherein the drain initialization transistor is not turned on in a normal mode in which the display panel is driven at a fixed frame frequency, and
wherein the drain initialization transistor is turned on to initialize the drain of the first transistor in a variable frequency mode in which the display panel is driven at

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Jihye
• Jin Jakyoung
• Kim Yu-Chol
• Yang Jin-Wook

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/325 Primary

  the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver · CPC title