Display panel, display panel test method, and display device

US12424129B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12424129-B2
Application numberUS-202217755526-A
CountryUS
Kind codeB2
Filing dateApr 18, 2022
Priority dateMar 28, 2022
Publication dateSep 23, 2025
Grant dateSep 23, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An embodiment of the present application provides a display panel, a display panel test method, and a display device. The display panel includes an underlay, signal lines and a first test module. The signal lines include first signal lines and second signal lines. The first signal lines are connected to first color pixels. The second signal lines are connected to second color pixels. first test module is disposed on underlay and are spaced from the signal lines. The first test module is connected to the first signal lines and the second signal lines.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising first color pixels and second color pixels, wherein the display panel comprises: an underlay; signal lines disposed on the underlay, wherein the signal lines comprise a plurality of first signal lines and a plurality of second signal lines, the first signal lines are connected to the first color pixels, and the second signal lines are connected to the second color pixels; and a first test module disposed on the underlay, wherein the first test module comprises a first shorting bar and a first soldering pad, an end of the first shorting bar is connected to the first signal lines and the second signal lines, another end of the first shorting bar is connected to the first soldering pad, and the first test module is configured for an array test of the display panel; wherein the display panel further comprises third color pixels, the signal lines further comprise a plurality of third signal lines, the third signal lines are connected to the third color pixels, the first test module further comprises a second shorting bar and a second soldering pad, an end of the second shorting bar is connected to the third signal lines, and another end of the second shorting bar is connected to the second soldering pad; wherein each of the first signal lines, the second signal lines, and the third signal lines is connected to the same ones of the first, second, or third color pixels instead of being connected to color pixels in different colors. 2. The display panel according to claim 1 , wherein the display panel further comprises a control module, the control module is connected to the first signal lines, the second signal lines, and the third signal lines, the control module is configured to control switching on/off of the first signal lines, the second signal lines, and the third signal lines. 3. The display panel according to claim 2 , wherein the control module comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor; and a gate electrode of the first thin film transistor is configured to receive a first trigger signal, a source electrode and a drain electrode of the first thin film transistor are connected to the first signal lines, a gate electrode of the second thin film transistor is configured to receive a second trigger signal, a source electrode and a drain electrode of the second thin film transistor are connected to the second signal lines, a gate electrode of the third thin film transistor is configured to receive a third trigger signal, and a source electrode and a drain electrode of the third thin film transistor are connected to the third signal lines. 4. The display panel according to claim 1 , wherein the display panel further comprises a second test module, the second test module is disposed on the underlay and is disposed at an interval from the first test module, the second test module comprises a first color shorting bar, a first color test soldering pad, a second color shorting bar, and a second color test soldering pad, an end of the first color shorting bar is electrically connected to the first signal lines, another end of the first color shorting bar is connected to the first color test soldering pad, an end of the second color shorting bar is electrically connected to the second signal lines, another end of the second color shorting bar is connected to the second color test soldering pad, and the first test module is disposed on a side of the second test module away from the first color pixels and the second color pixels. 5. The display panel according to claim 4 , wherein the second test module further comprises a third color shorting bar and a third color test soldering pad, an end of the third color shorting bar is electrically connected to the third signal lines, and another end of the third color shorting bar is connected to the third color test soldering pad. 6. The display panel according to claim 1 , wherein the first color pixels are blue pixels, the second color pixels are red pixels, and the third color pixels are green pixels. 7. The display panel according to claim 1 , wherein the first color pixels are red pixels, the second color pixels are green pixels, and the third color pixels are blue pixels. 8. The display panel according to claim 1 , wherein the first color pixels are green pixels, the second color pixels are blue pixels, and the third color pixels are red pixels. 9. A display panel test method, configured to test the display panel according to claim 1 , wherein the display panel test method comprises: implementing an array test to the display panel by an array test soldering pad in the first test module. 10. A display device, comprising a display panel and an encapsulation structure, wherein the display panel is the display panel according to claim 1 , and the encapsulation structure is disposed on the display panel. 11. The display device according to claim 10 , wherein the display panel further comprises a control module, the control module is connected to the first signal lines, the second signal lines and the third signal lines, the control module is configured to control switching on/off of the first signal lines, the second signal lines, and the third signal lines. 12. The display device according to claim 11 , wherein the control module comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor; and a gate electrode of the first thin film transistor is configured to receive a first trigger signal, a source electrode and a drain electrode of the first thin film transistor are connected to the first signal lines, a gate electrode of the second thin film transistor is configured to receive a second trigger signal, a source electrode and a drain electrode of the second thin film transistor are connected to the second signal lines, a gate electrode of the third thin film transistor is configured to receive a third trigger signal, and a source electrode and a drain electrode of the third thin film transistor are connected to the third signal lines. 13. The display device according to claim 10 , wherein the display panel further comprises second test module, the second test module is disposed on the underlay and is disposed at an interval from the first test module, the second test module comprises a first color shorting bar, a first color test soldering pad, a second color shorting bar, and a second color test soldering pad, an end of the first color shorting bar is electrically connected to the first signal lines, another end of the first color shorting bar is connected to the first color test soldering pad, an end of the second color shorting bar is electrically connected to the second signal lines, another end of the second color shorting bar is connected to the second color test soldering pad, and the first test module is disposed on a side of the second test module away from the first color pixels and the second color pixels. 14. The display device according to claim 13 , wherein the second test module further comprises a third color shorting bar and a third color test soldering pad, an end of the third color shorting bar is electrically connected to the third signal lines, and another end of the third color shorting bar is connected to the third color test soldering pad. 15. The display device according to claim 10 , wherein the first color pixels are blue pixels, the second color pixels are red pixels, and the third color pixels are green pixels. 16. The display device according to claim 10 , wherein the first color pixels are r

Assignees

Inventors

Classifications

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

  • comprising more than three subpixels, e.g. red-green-blue-white [RGBW] · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • comprising red-green-blue [RGB] subpixels · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12424129B2 cover?
An embodiment of the present application provides a display panel, a display panel test method, and a display device. The display panel includes an underlay, signal lines and a first test module. The signal lines include first signal lines and second signal lines. The first signal lines are connected to first color pixels. The second signal lines are connected to second color pixels. first test…
Who is the assignee on this patent?
Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 23 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).