Panel inspection circuit and liquid crystal display panel

Patent metadata

Field	Value
Publication number	US-2018180959-A1
Application number	US-201615312447-A
Country	US
Kind code	A1
Filing date	Jun 3, 2016
Priority date	Apr 21, 2016
Publication date	Jun 28, 2018
Grant date	—

Abstract

A panel inspection circuit is provided and includes: multiple data signal lines; multiple testing switches; multiple testing lines including: a first testing line, a second testing line and a third testing line; and multiple control lines including a first control line, a second control line and a third control line; the first control line is used to turn on the testing switches which are connected to the first testing line; the second control line is used to turn on the testing switches which are connected to the second testing line; the third control line is used to turn on the testing switches which are connected to the third testing line.

First claim

What is claimed is:

1 . A panel inspection circuit, comprising:
multiple data signal lines; multiple testing switches being connected to the data signal lines, respectively; wherein the testing switches are thin-film transistors; multiple testing lines being connected to the testing switches, and including: a first testing line for inputting a red sub-pixel testing signal to the testing switches; a second testing line for inputting a green sub-pixel testing signal to the testing switches; and a third testing line for inputting a blue sub-pixel testing signal to the testing switches; and multiple control lines being connected to the testing switches, and including a first control line, a second control line and a third control line; wherein the first control line is used to turn on the testing switches which are connected to the first testing line; the second control line is used to turn on the testing switches which are connected to the second testing line; the third control line is used to turn on the testing switches which are connected to the third testing line.

2 . The panel inspection circuit as claimed in claim 1 , wherein each of the testing switches has a source, a drain and a gate; the source is connected to a corresponding one of the testing lines; the drain is connected to a corresponding one of the data signal lines; and the gate is connected to a corresponding one of the control lines.

3 . The panel inspection circuit as claimed in claim 2 , wherein the testing signal inputted by each of the testing lines has a lowest display electric potential value.

4 . The panel inspection circuit as claimed in claim 3 , wherein each of the testing switches has a lowest activating electric potential value; the lowest activating electric potential value is lower than the lowest display electric potential value.

5 . The panel inspection circuit as claimed in claim 4 , wherein the panel inspection circuit further comprises a driving circuit assembly mounted on a substrate; wherein the driving circuit assembly is electrically connected the data signal lines.

6 . The panel inspection circuit as claimed in claim 5 , wherein each of the data signal lines has a metal terminal used to receive the corresponding testing signal.

7 . A panel inspection circuit, comprising:
multiple data signal lines; multiple testing switches being connected to the data signal lines, respectively; multiple testing lines being connected to the testing switches, and including: a first testing line for inputting a red sub-pixel testing signal to the testing switches; a second testing line for inputting a green sub-pixel testing signal to the testing switches; and a third testing line for inputting a blue sub-pixel testing signal to the testing switches; and multiple control lines being connected to the testing switches, and including a first control line, a second control line and a third control line; wherein the first control line is used to turn on the testing switches which are connected to the first testing line; the second control line is used to turn on the testing switches which are connected to the second testing line; the third control line is used to turn on the testing switches which are connected to the third testing line.

8 . The panel inspection circuit as claimed in claim 7 , wherein the testing switches are thin-film transistors.

9 . The panel inspection circuit as claimed in claim 8 , wherein each of the testing switches has a source, a drain and a gate; the source is connected to a corresponding one of the testing lines; the drain is connected to a corresponding one of the data signal lines; the gate is connected to a corresponding one of the control lines.

10 . The panel inspection circuit as claimed in claim 9 , wherein the testing signal inputted by each of the testing lines has a lowest display electric potential value.

11 . The panel inspection circuit as claimed in claim 10 , wherein each of the testing switches has a lowest activating electric potential value; the lowest activating electric potential value is lower than the lowest display electric potential value.

12 . The panel inspection circuit as claimed in claim 11 , wherein the panel inspection circuit further comprises a driving circuit assembly mounted on a substrate; wherein the driving circuit assembly is electrically connected the data signal lines.

13 . The panel inspection circuit as claimed in claim 12 , wherein each of the data signal lines has a metal terminal used to receive the corresponding testing signal.

14 . A liquid crystal display panel comprising a panel inspection circuit, wherein the panel inspection circuit includes:
multiple data signal lines; multiple testing switches being connected to the data signal lines, respectively; multiple testing lines being connected to the testing switches, and including: a first testing line for inputting a red sub-pixel testing signal to the testing switches; a second testing line for inputting a green sub-pixel testing signal to the testing switches; and a third testing line for inputting a blue sub-pixel testing signal to the testing switches; and multiple control lines being connected to the testing switches, and including a first control line, a second control line and a third control line; wherein the first control line is used to turn on the testing switches which are connected to the first testing line; the second control line is used to turn on the testing switches which are connected to the second testing line; the third control line is used to turn on the testing switches which are connected to the third testing line.

15 . The liquid crystal display panel as claimed in claim 14 , wherein the testing switches are thin-film transistors.

16 . The liquid crystal display panel as claimed in claim 15 , wherein each of the testing switches has a source, a drain and a gate; the source is connected to a corresponding one of the testing lines; the drain is connected to a corresponding one of the data signal lines; and the gate is connected to a corresponding one of the control lines.

17 . The liquid crystal display panel as claimed in claim 16 , wherein the testing signal inputted by each of the testing lines has a lowest display electric potential value.

18 . The liquid crystal display panel as claimed in claim 17 , wherein each of the testing switches has a lowest activating electric potential value; the lowest activating electric potential value is lower than the lowest display electric potential value.

19 . The liquid crystal display panel as claimed in claim 18 , wherein the panel inspection circuit further includes a driving circuit assembly mounted on a substrate; wherein the driving circuit assembly is electrically connected the data signal lines.

20 . The liquid crystal display panel as claimed in claim 19 , wherein each of the data signal lines has a metal terminal used to receive the corresponding testing signal.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Gan Qiming

Classifications

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F2001/136254

  Physics · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/1309 Primary

  Repairing; Testing · CPC title