Adaptive path based analysis process

Patent metadata

Field	Value
Publication number	US-12423504-B1
Application number	US-202217894236-A
Country	US
Kind code	B1
Filing date	Aug 24, 2022
Priority date	Aug 24, 2022
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

The present disclosure relates to a system and method for electronic design automation. Embodiments may include loading one or more libraries, netlists, or constraints associated with an electronic design and loading parasitic data associated with the electronic design. Embodiments may further include performing a self adaptive, infinite depth, path based analysis on at least a portion of the electronic design. Embodiments may also include analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis.

First claim

The invention claimed is:

1. A computer-implemented method comprising:
loading one or more libraries, netlists, or constraints associated with an electronic design;
loading parasitic data associated with the electronic design;
performing a self adaptive, infinite depth, path based analysis on one or more timing analysis views associated with the electronic design; and
analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis, wherein the self adaptive, infinite depth, path based analysis includes an endpoint violation level analysis; and
performing a full depth analysis for an endpoint having a high level violation, wherein performing a full depth analysis for an endpoint having a high level violation includes identifying all endpoint violations associated with the electronic design.

2. The computer-implemented method of claim 1 , wherein the self adaptive, infinite depth, path based analysis includes a clock period based identification process.

3. The computer-implemented method of claim 1 , wherein the self adaptive, infinite depth, path based analysis includes an explicit include or explicit exclude user-selectable option or a default.

4. The computer-implemented method of claim 1 , further comprising:
determining a plurality of paths for at least one high level violation endpoint.

5. The computer-implemented method of claim 1 , further comprising:
generating, using an adaptive learning engine, a self adaptive, infinite depth, path based analysis graph for one or more selective zones, one or more violating zones, one or more zones specific to a specified clock group, a user specified region, or an entire graph.

6. A computer-readable storage medium having stored thereon instructions that when executed by a machine result in the following operations:
loading one or more libraries, netlists, or constraints associated with an electronic design;
loading parasitic data associated with the electronic design;
performing a self adaptive, infinite depth, path based analysis on one or more timing analysis views associated with the electronic design; and
analyzing the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis, wherein the self adaptive, infinite depth, path based analysis includes an endpoint violation level analysis; and
performing a full depth analysis for an endpoint having a high level violation, wherein performing a full depth analysis for an endpoint having a high level violation includes identifying all endpoint violations associated with the electronic design.

7. The computer-readable storage medium of claim 6 , wherein the self adaptive, infinite depth, path based analysis includes a clock period based identification process.

8. The computer-readable storage medium of claim 6 , wherein the self adaptive, infinite depth, path based analysis includes an explicit include or explicit exclude user-selectable option or a default.

9. The computer-readable storage medium of claim 6 , further comprising:
determining a plurality of paths for at least one high level violation endpoint.

10. The computer-readable storage medium of claim 6 , further comprising:
generating, using an adaptive learning engine, a self adaptive, infinite depth, path based analysis graph for one or more selective zones, one or more violating zones, one or more zones specific to a specified clock group, a user specified region, or an entire graph.

11. A system comprising:
a computing device having at least one processor configured to load one or more libraries, netlists, or constraints associated with an electronic design, the at least one processor further configured to load parasitic data associated with the electronic design, the at least one processor further configured to perform a self adaptive, infinite depth, path based analysis on one or more timing analysis views associated with the electronic design and to analyze the electronic design based upon, at least in part, the self adaptive, infinite depth, path based analysis, wherein the self adaptive, infinite depth, path based analysis includes an endpoint violation level analysis, the at least one processor further configured to perform a full depth analysis for an endpoint having a high level violation, wherein performing a full depth analysis for an endpoint having a high level violation includes identifying all endpoint violations associated with the electronic design.

12. The system of claim 11 , wherein the self adaptive, infinite depth, path based analysis includes a clock period based identification process.

13. The system of claim 11 , wherein the self adaptive, infinite depth, path based analysis includes an explicit include or explicit exclude user-selectable option or a default.

Assignees

• Cadence Design Systems Inc

Inventors

• Gupta Umesh
• Agarwal Marut
• Patel Satyendra
• Kumar Naresh
• Sethia Prashant
• Sethi Ankit
• Kumar Shubham

Classifications

• G06F30/3312

  Timing analysis · CPC title

• G06F30/27

  using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title