Comprehensive path based analysis process

Patent metadata

Field	Value
Publication number	US-9875333-B1
Application number	US-201615001182-A
Country	US
Kind code	B1
Filing date	Jan 19, 2016
Priority date	Jan 19, 2016
Publication date	Jan 23, 2018
Grant date	Jan 23, 2018

Abstract

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis (“GBA”) violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis (“PBA”) on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

First claim

What is claimed is:

1. A computer-implemented method for comprehensive path based analysis in an electronic circuit design comprising:
receiving, using at least one processor, the electronic circuit design;
determining, using the at least one processor, one or more graph based analysis (“GBA”) violating nodes associated with the electronic design, wherein determining the one or more GBA violating nodes includes generating a timing graph associated with a given netlist and identifying a subset of nodes associated with the timing graph as GBA violating nodes;
identifying, using the at least one processor, a non-covered violating node from the GBA violating nodes;
determining, using the at least one processor, a worst timing path through the non-covered violating node;
invoking, using the at least one processor, a path-based analysis (“PBA”) on the worst timing path; and
determining, using the at least one processor, if the worst timing path satisfies the PBA.

2. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 1 , further comprising:
marking one or more nodes associated with the worst timing path as being covered based upon, at least in part, a comparison of GBA slack.

3. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 2 , wherein the comparison includes comparing a GBA slack of each node with a GBA slack of the worst timing path.

4. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 1 , further comprising:
after invoking the PBA, providing a user with every violating node through at least one path.

5. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 1 , further comprising:
generating one or more structural path collections for use during one or more of PBA and GBA, wherein the structural path collection is configured to include structural information associated with a timing path.

6. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 5 , wherein the one or more structural path collections are configured to enable path exclusion data collection before or after a change to the electronic design.

7. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 5 , wherein the structural information includes at least one of pin information and arc-related information.

8. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 1 , further comprising:
allowing a user to exclude at least one path associated with the electronic design from a reported path set.

9. The computer-implemented method for comprehensive path based analysis in an electronic circuit design of claim 1 , further comprising:
assigning a user-specified limit to a depth search associated with one or more post-PBA nodes; and
performing the depth search based upon, at least in part, the user-specified limit.

10. A system for comprehensive path based analysis in an electronic circuit design comprising:
a computing device having at least one processor configured to receive the electronic circuit design, the at least one processor further configured to determine one or more graph based analysis (“GBA”) violating nodes associated with the electronic design, wherein determining the one or more GBA violating nodes includes generating a timing graph associated with a given netlist and identifying a subset of nodes associated with the timing graph as GBA violating nodes, the at least one processor further configured to identify a non-covered violating node from the GBA violating nodes and to determine a worst timing path through the non-covered violating node, the at least one processor further configured to invoke a path-based analysis (“PBA”) on the worst timing path and to determine if the worst timing path satisfies the PBA.

11. The system for comprehensive path based analysis in an electronic circuit design of claim 10 , wherein the at least one processor is further configured to mark one or more nodes associated with the worst timing path as being covered based upon, at least in part, a comparison of GBA slack.

12. The system for comprehensive path based analysis in an electronic circuit design of claim 11 , wherein the comparison includes comparing a GBA slack of each node with a GBA slack of the worst timing path.

13. The system for comprehensive path based analysis in an electronic circuit design of claim 10 , wherein after invoking the PBA, the at least one processor is further configured to provide a user with every violating node through at least one path.

14. The system for comprehensive path based analysis in an electronic circuit design of claim 10 , the at least one processor is further configured to generate one or more structural path collections for use during one or more of PBA and GBA, wherein the structural path collection is configured to include structural information associated with a timing path.

15. The system for comprehensive path based analysis in an electronic circuit design of claim 14 , wherein the one or more structural path collections are configured to enable path exclusion data collection before or after a change to the electronic design.

16. The system for comprehensive path based analysis in an electronic circuit design of claim 14 , wherein the structural information includes at least one of pin information and arc-related information.

17. The system for comprehensive path based analysis in an electronic circuit design of claim 10 , wherein the at least one processor is further configured to allow a user to exclude at least one path associated with the electronic design from a reported path set.

18. The system for comprehensive path based analysis in an electronic circuit design of claim 10 , wherein the at least one processor is further configured to assign a user-specified limit to a depth search associated with one or more post-PBA nodes and to perform the depth search based upon, at least in part, the user-specified limit.

19. A computer-implemented method comprising:
receiving, using at least one processor, an electronic design;
determining, using the at least one processor, one or more graph based analysis (“GBA”) violating nodes associated with the electronic design;
identifying, using the at least one processor, a non-covered violating node from the GBA violating nodes;
determining, using the at least one processor, a worst timing path through the non-covered violating node;
invoking, using the at least one processor, a path-based analysis (“PBA”) on the worst timing path; and
determining, using the at least one processor, if the worst timing path satisfies the PBA.

20. The computer-implemented method of claim 19 , further comprising:
classifying at least one yet to be classified node associated with the electronic design into one of a plurality of possible categories;
marking the at least one node with the classified category; and
providing the marked node to a user.

Assignees

• Cadence Design Sysems Inc
• Cadence Design Systems Inc

Inventors

• Verma Sourabh Kumar
• Kumar Naresh
• Tomar Ajay
• Agarwal Rakesh
• Gupta Umesh
• Bansal Manish
• Guha Kaustav
• Sethia Prashant

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic