PCIe-based communications method and apparatus

Patent metadata

Field	Value
Publication number	US-12423261-B2
Application number	US-202217895769-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Feb 27, 2020
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A PCIe-based communications method includes: a root complex writes identity information of a second node into a first node and writes routing table information into a third node, where the first node is a source node of first data, the second node is a destination node of the first data, and the third node is a node through which the first data arrives at the second node.

First claim

What is claimed is:

1. A peripheral component interconnect express (PCIe)-based communications method, wherein the method comprises:
writing identity information of a second node into a first node, wherein the first node is a source node of first data, and the second node is a destination node of the first data;
writing routing table information into a third node, wherein the third node is a node through which the first data arrives at the second node; and
determining whether the first node supports a first working mode or whether the third node supports the first working mode, wherein the first working mode is a working mode in which communication between nodes does not use a root complex.

2. The method according to claim 1 , wherein the method further comprises:
determining that the first node supports the first working mode; or
determining that the first node supports the first working mode and a second working mode, wherein
the second working mode is a working mode in which communication between nodes uses the root complex.

3. The method according to claim 2 , wherein the method further comprises:
configuring a first memory address for the first node when the first node is in the second working mode, wherein the first memory address is a physical address in running memory corresponding to a central processing unit (CPU) to which local memory space of the first node is mapped.

4. The method according to claim 1 , wherein the method further comprises:
determining that the third node supports the first working mode; or
determining that the third node supports the first working mode and a second working mode, wherein
the second working mode is a working mode in which communication between nodes uses the root complex.

5. The method according to claim 4 , wherein the method further comprises:
configuring a second memory address for the third node when the third node is in the second working mode, wherein the second memory address is a physical address in running memory corresponding to a central processing unit (CPU) to which local memory space of the third node is mapped.

6. The method according to claim 1 , wherein the method further comprises:
writing identity information of the first node into the first node.

7. The method according to claim 1 , wherein the method further comprises:
writing identity information of the third node into the third node.

8. A peripheral component interconnect express (PCIe)-based communications apparatus, wherein the apparatus comprises:
a processor, configured to:
write identity information of a second node into a first node, wherein the first node is a source node of first data, and the second node is a destination node of the first data;
write routing table information into a third node, wherein the third node is a node through which the first data arrives at the second node; and
determine whether the first node supports a first working mode or whether the third node supports the first working mode, wherein the first working mode is a working mode in which communication between nodes does not use a root complex.

9. The apparatus according to claim 8 , wherein the processor is further configured to:
determine that the first node supports the first working mode; or
determine that the first node supports the first working mode and a second working mode, wherein
the second working mode is a working mode in which communication between nodes uses the root complex.

10. The apparatus according to claim 9 , wherein the processor is further configured to:
configure a first memory address for the first node when the first node is in the second working mode, wherein the first memory address is a physical address in running memory corresponding to a central processing unit (CPU) to which local memory space of the first node is mapped.

11. The apparatus according to claim 8 , wherein the processor is further configured to:
determine that the third node supports the first working mode; or
determine that the third node supports the first working mode and a second working mode, wherein
the second working mode is a working mode in which communication between nodes uses the root complex.

12. The apparatus according to claim 11 , wherein the processor is further configured to:
configure a second memory address for the third node when the third node is in the second working mode, wherein the second memory address is a physical address in running memory corresponding to a central processing unit (CPU) to which local memory space of the third node is mapped.

13. The apparatus according to claim 8 , wherein the processor is further configured to:
write identity information of the first node into the first node.

14. The apparatus according to claim 8 , wherein the processor is further configured to:
write identity information of the third node into the third node.

15. The apparatus according to claim 8 , wherein the identity information is a bus, device, and function number (BDF) or an identity (ID) number.

16. A peripheral component interconnect express (PCIe)-based communications apparatus, wherein the apparatus comprises:
a transceiver;
at least one processor; and
one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the communications apparatus to:
determine identity information of a second node based on information stored in a first node, wherein the second node is a destination node of first data; and
send, through the transceiver, a first transaction layer packet (TLP) to a third node, wherein the first TLP comprises the first data and the identity information of the second node, wherein the first node supports a first working mode, the first working mode is a working mode in which communication between nodes does not use a root complex.

17. The apparatus according to claim 16 , wherein the first node supports the first working mode and a second working mode, and the second working mode is a working mode in which communication between nodes uses the root complex.

18. The apparatus according to claim 16 , wherein the stored information further comprises identity information of the first node.

19. The apparatus according to claim 18 , wherein the first TLP further comprises the identity information of the first node.

Assignees

• Shenzhen Yinwang Intelligent Technology Co Ltd

Inventors

• Wan Lei
• Zhu Jiezuo
• Wang Xuehuan
• Bao Pengxin

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title