PCIe-Based Data Transmission Method and Apparatus

Patent metadata

Field	Value
Publication number	US-2022368564-A1
Application number	US-202217870406-A
Country	US
Kind code	A1
Filing date	Jul 21, 2022
Priority date	Jan 22, 2020
Publication date	Nov 17, 2022
Grant date	—

Abstract

A Peripheral Component Interconnect Express (PCIe)-based data transmission method includes a first node that encapsulates first data into a first transaction layer packet (TLP) and sends the first TLP to a second node, where a TLP header of the first TLP includes a first field, the first field is used to indicate a data type of the first data, and the data type includes at least one of the following: an image type, a video type, a control type, a security type, and a stream write (SWRITE) type. In embodiments of this application, the first field in the TLP header is used to indicate information required for data transmission, for example, the data type, so that nodes can communicate with each other without using a root complex.

First claim

1 . A Peripheral Component Interconnect Express (PCIe)-based data transmission method implemented by a first node, wherein the Pete-based data transmission method comprises:
encapsulating first data into a transaction layer packet (TLP), wherein the TLP comprises a TLP header comprising a first field, wherein the first field indicates a data type of the first data, and wherein the data type comprises at least one of an image type, a video type, a control type, a security type, or a stream write (SWRITE) type; and sending the TLP to a second node.

2 . The PCIe-based data transmission method of claim 1 , wherein the first field further indicates at least one piece of parameter information corresponding to the data type.

3 . The PCIe-based data transmission method of claim 1 , wherein the first field is a type field in the TLP header.

4 . The PCIe-based data transmission method of claim 1 , wherein the TLP header further comprises a second field indicating identity information of a third node, and wherein the third node is a destination device of the TLP.

5 . The PCIe-based data transmission method of claim 4 , wherein the second field further indicates at least one piece of parameter information corresponding to the data type.

6 . A Peripheral Component Interconnect Express (PCIe)-based data transmission apparatus comprising:
a processor configured to encapsulate first data into a transaction layer packet (TLP), wherein the TLP comprises a TLP header comprising, a first field, wherein the first field indicates a data type of the first data, and wherein the data type comprises at least one of an image type, a video type, a control type, a security type and, or a stream write (SWRITE) type; and a transceiver coupled to the processor and configured to send the first TLP to a second node.

7 . The PCIe-based data transmission apparatus of claim 6 , wherein the first field further indicates at least one piece of parameter information corresponding to the data type.

8 . The PCIe-based data transmission apparatus of claim 6 , wherein the first field is a type field in the TLP header.

9 . The PCIe-based data transmission apparatus of claim 6 , wherein the first field comprises a reserved value.

10 . The PCIe-based data transmission apparatus according of claim 6 , wherein the TLP header further comprises a second field indicating identity information of a third node, and wherein the third node is a destination device of the TLP.

11 . The PCIe-based data transmission apparatus of claim 10 , wherein the second field further indicates at least one piece of parameter information corresponding to the data type.

12 . The PCIe-based data transmission apparatus of claim 10 , wherein the second field is one or more bytes in the range of a byte 4 to a byte 15 in a 16-byte TLP header or one or more bytes in the range of a byte 4 to a byte 11 in a 12-byte TLP header.

13 . A Peripheral Component Interconnect Express (PCIe)-based data transmission apparatus comprising:
a transceiver configured to:
receive, from a first node, a first transaction layer packet (TLP) comprising first data; and
send, to a third node, a second TLP comprising the first data,
wherein the first TLP or the second TLP comprises a TLP header comprising a first field,
wherein the first field indicates a data type of the first data, and
wherein the data type comprises at least one of an image type, a video type, a control type, a security type, or a stream write (SWRITE) type.

14 . The PCIe-based data transmission apparatus according of claim 13 , wherein the first field further indicates at least one piece of parameter information corresponding to the data type.

15 . The PCIe-based data transmission apparatus of claim 13 , wherein the first field is a type field in the TLP header.

16 . The PCIe-based data transmission apparatus of claim 13 , wherein the first field comprises a reserved value.

17 . The PCIe-based data transmission apparatus of claim 13 , wherein the TLP header further comprises a second field indicating identity information of the third node.

18 . The PCIe-based data transmission apparatus of claim 17 , wherein the second field further indicates at least one piece of parameter information corresponding to the data type.

19 . The PCIe-based data transmission apparatus of claim 17 , wherein the second field is one or more bytes in the range of a byte 4 to a byte 15 in a 16-byte TLP header or one or more bytes in the range of a byte 4 to a byte 11 in a 12-byte TLP.

20 . The PCIe-based data transmission apparatus of claim 17 , further comprising a processor coupled to the transceiver and configured to determine a routing path based on the identity information of the third node, wherein the transceiver is further configured to send the second TLP to the third node based on the routing path.

Assignees

• Huawei Tech Co Ltd

Inventors

• Wan Lei
• Bao Pengxin

Classifications

• H04L45/306

  Route determination based on the nature of the carried application · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• G06F2213/0026

  PCI express · CPC title

• H04L12/4633 Primary

  Interconnection of networks using encapsulation techniques, e.g. tunneling · CPC title

• H04L45/74

  Address processing for routing · CPC title