Nonvolatile memory device and memory system

Patent metadata

Field	Value
Publication number	US-12423246-B2
Application number	US-202418601839-A
Country	US
Kind code	B2
Filing date	Mar 11, 2024
Priority date	Sep 21, 2023
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array configured to store original setting data;
a page buffer circuit connected to the memory cell array through a plurality of bit-lines;
a secure buffer including an access control circuit and a plurality of registers with restricted access, the plurality of registers configured to store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence; and
a control circuit configured to control the page buffer circuit and the secure buffer,
wherein the plurality of registers includes a first register and second registers, and
wherein the access control circuit is configured to access, in response to the first register being accessed, at least a portion of the second registers concurrently with accessing the first register.

2. The nonvolatile memory device of claim 1 , wherein the first register being accessed results in first setting data stored in the first register being changed, and
wherein the access control circuit is configured to change a respective setting data stored in each of the second registers by accessing the second registers concurrently with accessing the first register.

3. The nonvolatile memory device of claim 2 , wherein the access control circuit includes:
a first AND gate configured to generate a first selection signal for selecting the first register based on a register access mode signal and bits of a first register address designating the first register;
second AND gates configured to generate intermediate selection signals associated with selecting the second registers based on the register access mode signal and bits of second register addresses designating the second registers; and
OR gates configured to generate second selection signals for selecting a respective second register of the second registers by performing an OR operation on the first selection signal and a corresponding intermediate selection signal of the intermediate selection signals.

4. The nonvolatile memory device of claim 3 , wherein the first register is accessed and the first setting data stored in the first register is changed in response to an activation of the first selection signal, and
wherein the access control circuit is configured to change the respective setting data stored in each of the second registers by accessing the second registers concurrently with accessing the first register, by activating the second selection signals.

5. The nonvolatile memory device of claim 4 , wherein the access control circuit is configured to:
deactivate the first selection signal after the respective setting data stored in each of the second registers is changed, and
recover respective changed setting data in each of the second registers to a respective original setting data.

6. The nonvolatile memory device of claim 5 , wherein the control circuit is configured to perform a core operation based on the changed first setting data and the recovered respective original setting data stored in the first register and the second registers.

7. The nonvolatile memory device of claim 1 , wherein the access control circuit is configured to:
group the second registers into at least two groups;
when the first register is accessed and first setting data stored in the first register is changed, access a first group of the at least two groups concurrently with accessing the first register; and
change setting data stored in at least one register of the first group.

8. The nonvolatile memory device of claim 7 , wherein the access control circuit includes:
a first AND gate configured to generate a first selection signal for selecting the first register based on a register access mode signal and bits of a first register address designating the first register;
second AND gates configured to generate intermediate selection signals associated with selecting the second registers based on the register access mode signal and bits of second register addresses designating the second registers;
third AND gates configured to generate group selection signals for selecting respective groups of the at least two groups based on group selection information that is based on a combination of consecutive commands; and
OR gates configured to generate second selection signals for selecting a respective second register of the second registers by performing an OR operation on the first selection signal, a corresponding group selection signal of the group selection signals, and a corresponding intermediate selection signal of the intermediate selection signals.

9. The nonvolatile memory device of claim 8 , wherein the at least two groups include the first group and a second group, and
wherein the access control circuit is configured to change, when the first register is accessed and the first setting data stored in the first register is changed in response to an activation of the first selection signal, setting data stored in at least one second register in the first group by activating a first group selection signal of the group selection signals.

10. The nonvolatile memory device of claim 9 , wherein the access control circuit is configured to:
deactivate the first selection signal after the setting data stored in the at least one second register is changed,
select the at least one second register, and
recover the changed setting data in the at least one second register to the original setting data.

11. The nonvolatile memory device of claim 8 , wherein the at least two groups include the first group and a second group, and
wherein the access control circuit is configured to change, when the first register is accessed and the first setting data stored in the first register is changed in response to an activation of the first selection signal, setting data stored in at least one second register in the second group by activating a second group selection signal of the group selection signals.

12. The nonvolatile memory device of claim 11 , wherein the access control circuit is configured to:
deactivate the first selection signal after the setting data stored in the at least one second register is changed,
select the at least one second register, and
recover the changed setting data in the at least one second register to the original setting data.

13. The nonvolatile memory device of claim 1 , wherein the access control circuit is configured to, when the first register is accessed and first setting data stored in the first register is changed:
cut off access to the second registers based on being configured in a first mode; or
change a respective setting data stored in each of the second registers by accessing the second registers concurrently with accessing the first register based on being configured in a second mode.

14. The nonvolatile memory device of claim 1 , wherein the access control circuit includes:
a first AND gate configured to generate a first mode selection signal that is activated in a first mode based on a setting data dump signal designating the first mode, a register access mode signal, and bits of a first register address designating the first register;
a second AND gate configured to generate a second mode selection signal that is activated in a second mode based on a pin reduction mode signal designating the second mode, the register access mode signal, and the bits of the first register address;
third AND gates configured to generate intermediate selection signals associated with selecting the second registers based on the register access mode signal and bits second register

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hanjun
• Kim Suyong
• Lee Seungjae
• Jeon Suchang

Classifications

• G06F3/0622

  in relation to access · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title