Memory devices with multiple sets of latencies and methods for operating the same

Patent metadata

Field	Value
Publication number	US-12423010-B2
Application number	US-202418444215-A
Country	US
Kind code	B2
Filing date	Feb 16, 2024
Priority date	Oct 30, 2017
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

First claim

What is claimed is:

1. A method of operating a dynamic random access memory (DRAM) device, comprising:
determining a quantity of operating features that are enabled from a plurality of operating features supported by the DRAM device, the quantity of enabled operating features comprising a byte mode feature associated with operation of the DRAM device, a read data copy feature associated with operation of the DRAM device, or both;
selecting a set of latency values from a plurality of sets of latency values based at least in part on the quantity of operating features that are enabled, wherein the plurality of sets of latency values is selected based at least in part on whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled at the DRAM device;
selecting a latency value from the set of latency values based at least in part on a value of a mode register; and
executing a read command based at least in part on the selected latency value.

2. The method of claim 1 , wherein:
the plurality of sets of latency values comprises a plurality of first values associated with the DVFS being enabled; and
a second plurality of sets of latency values comprises a plurality of second values, different than the plurality of first values, that are associated with the DVFS being disabled.

3. The method of claim 1 , wherein the value of the mode register comprises a four-bit value that indicates the latency value from the set of latency values.

4. The method of claim 1 , wherein the set of latency values comprises a plurality of latency values that each correspond to a respective mode register setting from a plurality of mode register settings of the DRAM device.

5. The method of claim 1 , wherein the value of the mode register is associated with a lower limit for a clock signal and an upper limit for the clock signal.

6. The method of claim 5 , further comprising:
operating the DRAM device at a frequency that is greater than or equal to the lower limit for the clock signal and that is less than or equal to the upper limit for the clock signal.

7. The method of claim 5 , further comprising:
setting the value of the mode register based at least in part on the lower limit for the clock signal and the upper limit for the clock signal.

8. The method of claim 1 , wherein the set of latency values comprises a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the DRAM device.

9. A dynamic random access memory (DRAM) device, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the DRAM device to:
determine a quantity of operating features that are enabled from a plurality of operating features supported by the DRAM device, the quantity of enabled operating features comprising a byte mode feature associated with operation of the DRAM device, a read data copy feature associated with operation of the DRAM device, or both;
select a set of latency values from a plurality of sets of latency values based at least in part on the quantity of operating features that are enabled, wherein the plurality of sets of latency values is selected based at least in part on whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled at the DRAM device;
select a latency value from the set of latency values based at least in part on a value of a mode register; and
execute a read command based at least in part on the selected latency value.

10. The DRAM device of claim 9 , wherein:
the plurality of sets of latency values comprises a plurality of first values associated with the DVFS being enabled; and
a second plurality of sets of latency values comprises a plurality of second values, different than the plurality of first values, associated with the DVFS being disabled.

11. The DRAM device of claim 9 , wherein the value of the mode register comprises a four-bit value that indicates the latency value from the set of latency values.

12. The DRAM device of claim 9 , wherein the set of latency values comprises a plurality of latency values that each correspond to a respective mode register setting from a plurality of mode register settings of the DRAM device.

13. The DRAM device of claim 9 , wherein the value of the mode register is associated with a lower limit for a clock signal and an upper limit for the clock signal.

14. The DRAM device of claim 13 , wherein the one or more processors are individually or collectively further operable to execute the code to cause the DRAM device to:
operate the DRAM device at a frequency that is greater than or equal to the lower limit for the clock signal and that is less than or equal to the upper limit for the clock signal.

15. The DRAM device of claim 13 , wherein the one or more processors are individually or collectively further operable to execute the code to cause the DRAM device to:
set the value of the mode register based at least in part on the lower limit for the clock signal and the upper limit for the clock signal.

16. The DRAM device of claim 9 , wherein the set of latency values comprises a plurality of latency values that each correspond to a clock ratio from a plurality of clock ratios of the DRAM device.

17. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
determine a quantity of operating features that are enabled from a plurality of operating features supported by a dynamic random access memory (DRAM) device, the quantity of enabled operating features comprising a byte mode feature associated with operation of the DRAM device, a read data copy feature associated with operation of the DRAM device, or both;
select a set of latency values from a plurality of sets of latency values based at least in part on the quantity of operating features that are enabled, wherein the plurality of sets of latency values is selected based at least in part on whether dynamic voltage and frequency scaling (DVFS) is disabled or enabled at the DRAM device;
select a latency value from the set of latency values based at least in part on a value of a mode register; and
execute a read command based at least in part on the selected latency value.

18. The non-transitory computer-readable medium of claim 17 , wherein:
the plurality of sets of latency values comprises a plurality of first values associated with the DVFS being enabled; and
a second plurality of sets of latency values comprises a plurality of second values, different than the plurality of first values, associated with the DVFS being disabled.

19. The non-transitory computer-readable medium of claim 17 , wherein the value of the mode register comprises a four-bit value that indicates the latency value from the set of latency values.

20. The non-transitory computer-readable medium of claim 17 , wherein the set of latency values comprises a plurality of latency values that each correspond to a respective mode register setting from a plurality of mode register settings of the DRAM device.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Gans Dean D
• Riho Yoshiro
• Saito Shunichi
• Nagashima Osamu

Classifications

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C2207/2272

  Latency related aspects · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0611

  in relation to response time · CPC title