Semiconductor device, semiconductor system, and method for use in operating the same based on operation mode information

Patent metadata

Field	Value
Publication number	US-2016372171-A1
Application number	US-201514885702-A
Country	US
Kind code	A1
Filing date	Oct 16, 2015
Priority date	Jun 16, 2015
Publication date	Dec 22, 2016
Grant date	—

Abstract

A semiconductor device includes a flag signal generating circuit, a reference voltage generating circuit, and a first buffer. The flag signal generating circuit generates a flag signal based on an internal command and a training control code which are extracted from an external signal. The reference voltage generating circuit receives a set code based on the flag signal, an input control code and an output control code, and generates a reference voltage whose level is set based on the set code. The first buffer buffers the external signal based on the reference voltage to generate an internal signal, and generates a calibration code from the internal signal based on the flag signal to output the calibration code.

First claim

1 . A semiconductor device comprising:
a flag signal generating circuit to generate a flag signal based on an internal command and a training control code which are extracted from an external signal; a reference voltage generating circuit to receive a set code based on the flag signal, an input control code and an output control code, and to generate a reference voltage having a level that is set based on the set code; and a buffer to buffer the external signal based on the reference voltage for generating an internal signal, and to generate a calibration code from the internal signal based on the flag signal for outputting the calibration code.

2 . The device of claim 1 , wherein the flag signal generating circuit generates the flag signal based on the internal command and the training control code which are extracted from the external signal which includes at least one of a command and an address.

3 . The device of claim 1 , wherein the set code is inputted as a first data signal and the calibration code is outputted as a second data signal.

4 . The device of claim 1 , wherein the buffer comprises a first buffer, the device further comprising:
a second buffer to buffer an external clock signal and a chip selection signal for generating an internal clock signal and an internal chip selection signal.

5 . The device of claim 4 , wherein the first buffer includes:
a first latch to latch the internal chip selection signal based on the flag signal for generating an internal latch signal; and a second latch to generate the calibration code from the internal signal based on the internal latch signal.

6 . The device of claim 5 , wherein the second latch includes:
a transmitter to transmit the internal signal based on the internal latch signal; and an initialization circuit to initialize an output node of the transmitter based on a power-up signal.

7 . The device of claim 1 , further comprising:
a training control signal generating circuit to generate a training control signal based on the flag signal and a clock enablement signal.

8 . The device of claim 1 , wherein the reference voltage generating circuit receives information included in the set code for each frequency of an external clock signal based on the input control code and the output control code while the flag signal is enabled, and to set a level of the reference voltage from the information included in the set code which is inputted for each frequency of the external clock signal.

9 . The device of claim 8 , wherein the reference voltage generating circuit receives and stores first information included in the set code for setting the reference voltage at a first set frequency of the external clock signal, the reference voltage to a first level using the stored first information, receives and stores second information included in the set code for setting the reference voltage at a second set frequency of the external clock signal, and set the reference voltage to a second level using the stored second information.

10 . The device of claim 1 , wherein the reference voltage generating circuit includes:
an input/output control signal generating circuit to generate a first input control signal, a second input control signal, a first output control signal and a second output control signal based on the input control code and the output control code, while the flag signal is enabled; a first storage to store first information included in the set code for setting the reference voltage at a first set frequency of an external clock signal based on the first input control signal and the first output control signal, and to output the stored first information as a first storage signal for setting the level of the reference voltage; and a second storage to store second information included in the set code for setting the reference voltage at a second set frequency of the external clock signal based on the second input control signal and the second output control signal, and to output the stored second information as a second storage signal for setting the level of the reference voltage.

11 . The device of claim 10 ,
wherein the first input control signal is enabled if a combination of the input control code and the output control code is a first logic level combination; wherein the first output control signal is enabled if the combination of the input control code and the output control code is a second logic level combination; wherein the second input control signal is enabled if the combination of the input control code and the output control code is a third logic level combination; and wherein the second output control signal is enabled if the combination of the input control code and the output control code is a fourth logic level combination.

12 . The device of claim 10 , wherein the first storage stores the first information if the first input control signal is enabled, and outputs the stored first information as the first storage signal if the first output control signal is enabled.

13 . A semiconductor device comprising:
an input/output control signal generating circuit to generate a first input control signal, a second input control signal, a first output control signal and a second output control signal based on an input control code and an output control code, while a flag signal is enabled; a first storage to store first information included in a set code for setting a reference voltage at a first set frequency of an external clock signal based on the first input control signal and the first output control signal, and to output the stored first information as a first storage signal for setting operation mode information; and a second storage to store second information included in the set code for setting the reference voltage at a second set frequency of the external clock signal based on the second input control signal and the second output control signal, and to output the stored second information as a second storage signal for setting the operation mode information.

14 . The device of claim 13 , further comprising:
a flag signal generating circuit to generate the flag signal based on an internal command and a training control code which are extracted from an external signal.

15 . The device of claim 13 ,
wherein the first input control signal is enabled if a combination of the input control code and the output control code is a first logic level combination; wherein the first output control signal is enabled if the combination of the input control code and the output control code is a second logic level combination; wherein the second input control signal is enabled if the combination of the input control code and the output control code is a third logic level combination; and wherein the second output control signal is enabled if the combination of the input control code and the output control code is a fourth logic level combination.

16 . The device of claim 13 , wherein the first storage stores the first information if the first input control signal is enabled, and outputs the stored first information as the first storage signal if the first output control signal is enabled.

17 . The device of claim 13 , wherein the operation mode information includes at least one of burst type information, burst length information, write latency information, read latency information, preamble information, postamble information, driver strength information, data bus inversion (DBI) information and on-die termination (ODT) information.

18 . A semiconductor system co

Assignees

• Sk Hynix Inc

Inventors

• Ko Bok Rim

Classifications

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/20

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title