Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-12419119-B2
Application number	US-202117796858-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Feb 21, 2020
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A solid-state imaging device includes an N-type semiconductor layer, an element layer including a photoelectric conversion element and an active element, an interconnect layer providing an interconnect for the active element, and an element isolation trench penetrating the semiconductor layer. The element layer includes a P-type region and an N-type region. A first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer. A second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench. The P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer.

First claim

The invention claimed is:

1. A solid-state imaging device including a pixel array of a plurality of unit pixels,
each of the plurality of unit pixels including a photoelectric conversion element that generates a signal charge by photoelectric conversion, and an active element that converts the signal charge into an electric signal and outputs the electric signal, the solid-state imaging device comprising:
an N-type semiconductor layer;
an element layer stacked on the semiconductor layer and including the photoelectric conversion element and the active element;
an interconnect layer stacked on the element layer and providing an interconnect for the active element; and
an element isolation trench penetrating the semiconductor layer, wherein
the element layer includes a P-type region and an N-type region,
a first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer,
a second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench,
the P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer,
the solid-state imaging device is configured as a semiconductor chip,
the element isolation trench includes, at a peripheral edge of the semiconductor chip, a near-edge element isolation trench that is continuous along an outer peripheral end, and
the near-edge element isolation trench has a polygonal shape with an obtuse angle in a plan view.

2. A solid-state imaging device including a pixel array of a plurality of unit pixels,
each of the plurality of unit pixels including a photoelectric conversion element that generates a signal charge by photoelectric conversion, and an active element that converts the signal charge into an electric signal and outputs the electric signal, the solid-state imaging device comprising:
an N-type semiconductor layer;
an element layer stacked on the semiconductor layer and including the photoelectric conversion element and the active element;
an interconnect layer stacked on the element layer and providing an interconnect for the active element; and
an element isolation trench penetrating the semiconductor layer, wherein
the element layer includes a P-type region and an N-type region,
a first hole storage layer is formed on a surface of the semiconductor layer on a side opposite to the element layer,
a second hole storage layer is formed in contact portions of the semiconductor layer and the element layer with the element isolation trench,
the P-type region of the element layer and the first hole storage layer are connected to each other by the second hole storage layer,
a P-type well region is formed on a periphery of the pixel array,
the element isolation trench includes a near-array element isolation trench formed in the P-type well region and surrounding the pixel array, and
the near-array element isolation trench surrounds the pixel array, in a polygonal shape with an obtuse angle in a plan view.

Assignees

• Tower Partners Semiconductor Co Ltd
• Tower Semiconductor Ltd

Inventors

• Oda Masahiro
• Takahashi Hiroki
• Doi Hiroyuki
• Otsuki Hirohisa

Classifications

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10F39/151 Primary

  Geometry or disposition of pixel elements, address lines or gate electrodes · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H10F39/157 Primary

  CCD or CID infrared image sensors · CPC title