Field effect transistor device

Patent metadata

Field	Value
Publication number	US-12419082-B2
Application number	US-202117997556-A
Country	US
Kind code	B2
Filing date	Dec 1, 2021
Priority date	Sep 6, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

The present invention discloses a field effect transistor device for improving the problem of the short-channel effect of a field effect transistor in the prior art, comprising: an active layer, comprising a source region, a drain region, and a channel region located between the source region and the drain region; a gate provided around the channel region; and a gate insulating layer provided between the gate and the channel region; wherein when a device is turned on, an effective channel, and an equivalent source and/or equivalent drain away from the effective channel are formed in the channel region, and the field effect transistor device connects the source region and the drain region through the effective channel, and the equivalent source and/or equivalent drain to contribute an operating current.

First claim

What is claimed is:

1. A field effect transistor device, comprising:
an active layer including a source region, a drain region, and a channel region located between the source region and the drain region;
a gate provided around the channel region; and
a gate insulating layer provided between the gate and the channel region;
wherein an effective channel, as well as an equivalent source and/or equivalent drain spaced away from the effective channel are formed in the channel region upon turning on of the field effect transistor device,
when the effective channel and the equivalent source are formed in the channel region, the source region is connected with the drain region through the equivalent source and the effective channel, so as to form an operating current;
when the effective channel and the equivalent drain are formed in the channel region, the source region is connected with the drain region through the effective channel and the equivalent drain, so as to form an operating current; and
when the effective channel, the equivalent source and the equivalent drain are formed in the channel region, the source region is connected with the drain region through the equivalent source, effective channel and the effective drain, so as to form an operating current;
wherein a conductive region that does not connect the source region and the drain region is formed in the channel region;
when the conductive region is in connection with the source region, the conductive region constitutes the equivalent source; and when the conductive region is in connection with the drain region, the conductive region constitutes the equivalent drain;
wherein perpendicular projections of the gate and the conductive region on a reference plane overlap, the gate is capable of controlling the channel region and form a channel therein, and portions of perpendicular projections of the gate and the conductive region on the reference plane that are not overlapping each other constitute the effective channel, wherein the reference plane is a plane passing through a central axis along a length direction of the channel region; and
wherein when the device is turned on, a conductance of the conductive region is greater than that of the rest portion of the channel other than the effective channel so that at least one of the conductive region and the effective channel can inject carriers into the other.

2. The field effect transistor device of claim 1 , wherein the conductance of the conductive region is at least greater than three times of the conductance of the rest portion of the channel other than the effective channel when the device is turned on.

3. The field effect transistor device of claim 1 , wherein a conductance per unit length of the effective channel in the channel is greater than the conductance per unit length of a rest portion of the channel other than the effective channel when the device is turned on.

4. The field effect transistor device of claim 3 , wherein the conductance per unit length of the effective channel in the channel is at least greater than three times of the conductance per unit length of a rest portion of the channels other than the effective channel when the device is turned on.

5. The field effect transistor device of claim 3 , wherein a thickness of a portion of the gate insulating layer corresponding to the effective channel is less than the thickness of the rest portion of the gate insulating layer.

6. The field effect transistor device of claim 3 , wherein a portion of the gate insulating layer corresponding to the effective channel and the rest portion of the gate insulating layer are made of materials with different dielectric constants.

7. The field effect transistor device of claim 3 , wherein a portion of the gate corresponding to the effective channel and the rest portion are made of materials having different work functions.

8. The field effect transistor device of claim 1 , wherein the equivalent source and/or equivalent drain extend along a central axis along a length direction of the channel region.

9. The field effect transistor device of claim 1 , wherein the conductive region is formed by a layer of carriers introduced by doping in the channel region.

10. The field effect transistor device of claim 1 , wherein the active layer comprises at least two semiconductor materials that change along an axial direction or a radial direction of the active layer.

11. The field effect transistor device of claim 1 , wherein an insulating structure is provided in the channel region, wherein the conductive region is formed by a layer of carriers induced in the channel region approximate to the insulating structure, said carriers being induced through electrostatic induction by electric charges introduced into the insulating structure.

12. The field effect transistor device of claim 1 , wherein a semiconductor structure is provided in the channel region, the semiconductor structure and the channel region form a heterostructure, and the conductive region is composed of a two-dimensional electron gas channel or a two-dimensional hole gas channel formed in the heterostructure.

13. The field effect transistor device of claim 1 , wherein the active layer is configured as a nanowire, nanosheet, or nanoring.

Assignees

• Univ Soochow

Inventors

• Wang Mingxiang
• Chen Lekai
• Zhang Dongli
• Wang Huaisheng

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title