Barrier structure configured to increase performance of III-V devices

Patent metadata

Field	Value
Publication number	US-12419074-B2
Application number	US-202217881984-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Jan 31, 2020
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

First claim

What is claimed is:

1. An integrated chip, comprising:
an undoped layer overlying a substrate;
a first barrier layer overlying the undoped layer;
a doped layer overlying the first barrier layer; and
a second barrier layer overlying the first barrier layer, wherein the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance, wherein the first and second barrier layers comprise a same III-V semiconductor material, wherein a first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer, wherein the first barrier layer comprises a first segment having a first thickness below the doped layer and a second segment having a second thickness directly adjacent to the first segment, wherein the second barrier layer has a third thickness, wherein the first thickness is greater than the second thickness and the third thickness, wherein the first segment has a top surface contacting a bottom surface of the doped layer and the second segment has a top surface contacting a bottom surface of the second barrier layer, wherein a bottom surface of the first segment is aligned with a bottom surface of the second segment, wherein the first segment contacts an inner sidewall of the second barrier layer.

2. The integrated chip according to claim 1 , wherein the first element is aluminum.

3. The integrated chip according to claim 1 , wherein the same III-V semiconductor material is aluminum gallium nitride.

4. The integrated chip according to claim 1 , wherein the first thickness of the first segment is defined between a bottom surface of the first barrier layer and the bottom surface of the doped layer, wherein the second thickness of the second segment is defined between the bottom surface of the first barrier layer and the bottom surface of the second barrier layer.

5. The integrated chip according to claim 1 , wherein the bottom surface of the second barrier layer is disposed below a top surface of the first barrier layer by a first distance, wherein a height of the second barrier layer above the top surface of the first barrier layer is less than the first distance.

6. The integrated chip according to claim 1 , wherein the second thickness is greater than the third thickness.

7. The integrated chip according to claim 1 , further comprising:
a gate electrode overlying the doped layer;
a first contact overlying the second barrier layer; and
a second contact overlying the second barrier layer, wherein the first and second contacts are separated from one another by the doped layer.

8. The integrated chip according to claim 1 , further comprising:
a passivation layer overlying the first barrier layer, wherein the passivation layer comprises a U-shaped segment arranged between the doped layer and the inner sidewall of the second barrier layer.

9. An integrated chip, comprising:
a buffer layer overlying a substrate;
an undoped binary III-V semiconductor layer overlying the buffer layer;
a doped binary III-V semiconductor layer overlying the undoped binary III-V semiconductor layer, wherein the doped binary III-V semiconductor layer is disposed within a middle region of the substrate and comprises a first outer sidewall opposite a second outer sidewall; and
a barrier structure overlying the undoped binary III-V semiconductor layer, wherein the barrier structure comprises a III-V semiconductor material with a first element, wherein an atomic concentration of the first element discretely increases at a first point along a first direction that extends from the middle region to a peripheral region adjacent to the middle region, wherein the first direction points away from the doped binary III-V semiconductor layer, wherein a lateral distance between the first point and the first outer sidewall of the doped binary III-V semiconductor layer facing the first direction is greater than a distance between the first and second outer sidewalls of the doped binary III-V semiconductor layer, wherein the barrier structure comprises:
a first barrier layer disposed between the undoped binary III-V semiconductor layer and the doped binary III-V semiconductor layer, wherein the first barrier layer comprises the III-V semiconductor material; and
a second barrier layer overlying the first barrier layer, wherein the second barrier layer is laterally offset from the middle region, wherein the second barrier layer comprises the III-V semiconductor material with a higher atomic concentration of the first element relative to the first barrier layer, wherein the first barrier layer contacts opposing inner sidewalls of the second barrier layer that are offset from the first and second outer sidewalls of the doped binary III-V semiconductor layer.

10. The integrated chip according to claim 9 , wherein a thickness of the barrier structure discretely increases along the first direction.

11. The integrated chip according to claim 9 , wherein the first element is aluminum.

12. The integrated chip according to claim 9 , further comprising:
a first contact overlying the barrier structure and within the peripheral region, wherein the first contact is on a first side of the doped binary III-V semiconductor layer; and
a second contact overlying the barrier structure and within the peripheral region, wherein the second contact is on a second side of the doped binary III-V semiconductor layer, wherein the first side is opposite the second side.

13. The integrated chip according to claim 12 , wherein the atomic concentration of the first element directly underlying the doped binary III-V semiconductor layer is less than the atomic concentration of the first element directly underlying the first and second contacts.

14. The integrated chip according to claim 12 , wherein bottom surfaces of the first and second contacts are disposed above a bottom surface of the doped binary III-V semiconductor layer.

15. The integrated chip according to claim 14 , wherein the bottom surfaces of the first and second contacts are disposed below a top surface of the doped binary III-V semiconductor layer.

16. An integrated chip, comprising:
an undoped layer overlying a substrate;
a first barrier layer overlying and directly contacting the undoped layer, wherein the first barrier layer comprises a first III-V semiconductor material having a first concentration of elements;
a doped layer overlying and directly contacting the first barrier layer; and
a second barrier layer overlying and directly contacting the first barrier layer, wherein the second barrier layer comprises the first III-V semiconductor material having a second concentration of elements different from the first concentration of elements, wherein the doped layer is spaced laterally between opposing sidewalls of the second barrier layer, wherein a first thickness of the first barrier layer is greater than a second thickness of the second barrier layer, wherein the second barrier layer directly contacts a first sidewall of the first barrier layer, wherein the first sidewall of the first barrier layer is laterally offset from the doped layer by a lateral distance.

17. The integrated chip of claim 16 , wherein the first barrier layer comprises a first atomic percentage of aluminum and the second barrier layer comprises a second atomic percentage of aluminum less than the first atomic percentage, wherein the first atomic percentage is within a range of about 7 to 25 percent and the second atomic percentage is within a range of about 10 to 60 perc

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Yun-Hsiang
• Tsai Chun Lin
• Yu Jiun-Lei Jerry
• Chen Po-Chih
• Yeh Chia-Ling
• Chen Ching Yu

Classifications

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title