Memory circuitry and method used in forming memory circuitry

Patent metadata

Field	Value
Publication number	US-12419048-B2
Application number	US-202217751978-A
Country	US
Kind code	B2
Filing date	May 24, 2022
Priority date	May 24, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating different-composition first tiers and second tiers, the stack comprising lower channel-material strings extending through the first tiers and the second tiers, a sacrificial plug comprising a sacrificial material directly above of individual ones of the lower channel-material strings;
removing the sacrificial material from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally along 45 degrees than orthogonally along 90 degrees relative to a sidewall of individual ones of the corner regions and in a greater amount than orthogonally vertical relative to a top of the individual ones of the corner regions;
forming an insulator material in void spaces left from the removing;
after forming the insulator material, removing remaining volume of the sacrificial plug; and
forming a channel material of upper channel-material strings below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings.

2. The method of claim 1 wherein the removing of the sacrificial material from the laterally-opposing corner regions comprises etching.

3. The method of claim 2 wherein the etching is isotropic.

4. The method of claim 1 wherein the sacrificial material comprises silicon nitride and polysilicon.

5. The method of claim 4 wherein the silicon nitride is laterally-outside of the polysilicon, the polysilicon comprising a laterally-outer portion and a laterally-inner portion, the laterally-outer portion comprising a greater quantity of a dopant therein as compared to quantity of the dopant, if any, in the laterally-inner portion.

6. The method of claim 1 wherein the sacrificial material comprises an insulating material of different composition from that of the insulator material, some of the insulating material remaining laterally-outside of the insulator material in a finished-circuitry construction.

7. The method of claim 6 wherein the insulator material comprises silicon dioxide and the insulating material comprises silicon nitride.

8. The method of claim 1 wherein the channel material of the upper channel-material strings is formed directly against the lower surfaces of the insulator material.

9. The method of claim 1 comprising forming the channel material of the upper channel-material strings directly against tops of the channel material of the lower channel-material strings.

10. The method of claim 1 wherein the sacrificial material comprises doped semiconductive material, a dopant of the doped semiconductive material facilitating the removing of the greater amount diagonally along 45° than orthogonally along 90° relative to a sidewall of the individual ones of the corner regions and in the greater amount than orthogonally vertical relative to the top of the individual ones of the corner regions.

11. The method of claim 10 wherein a laterally-outer portion of the sacrificial material comprises greater quantity of the dopant than quantity of the dopant, if any, in a laterally-inner portion of the sacrificial material.

12. The method of claim 11 wherein the laterally-outer portion comprises a laterally-outermost part and a laterally-innermost part each of which comprises the dopant, the laterally-outermost part of the laterally-outer portion comprising greater quantity of the dopant than the laterally-innermost part of the laterally-outer portion.

13. The method of claim 12 wherein the laterally-outer part and the laterally-inner part comprise polysilicon, the dopant comprises phosphorus, and the removing of the sacrificial material from the laterally-opposing corner regions comprises etching.

14. The method of claim 13 wherein the sacrificial material comprises silicon nitride laterally-outward of the laterally-outer part, some of the silicon nitride remaining laterally-outside of the insulator material in a finished-circuitry construction.

15. The method of claim 1 wherein, the lower channel-material strings comprise strings of memory cells in a finished-circuitry construction and the upper channel-material strings comprise select gate transistors in the finished-circuitry construction; and
individual ones of the upper channel-material strings comprise a corner region having horizontal and vertical converging segments, channel material of the individual ones of the upper channel-material strings in the corner region of the individual ones of the upper channel-material strings having a maximum 45-degree thickness taken from an outer apex of the corner region of 0.8 to 1.3 times a greater of a maximum vertical thickness of the horizontal segment and a maximum horizontal thickness of the vertical segment.

16. The method of claim 15 wherein the maximum 45-degree thickness is at least as great as the greater of the maximum vertical thickness of the horizontal segment and the maximum horizontal thickness of the vertical segment.

17. The method of claim 15 wherein the maximum 45-degree thickness is equal to the greater of the maximum vertical thickness of the horizontal segment and the maximum horizontal thickness of the vertical segment.

Assignees

• Micron Technology Inc

Inventors

• Howder Collin
• Kim Taehyun

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title