Analog-to-digital conversion with bit skipping functionality

Patent metadata

Field	Value
Publication number	US-12418303-B2
Application number	US-202117406704-A
Country	US
Kind code	B2
Filing date	Aug 19, 2021
Priority date	Aug 19, 2021
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

Techniques for performing analog-to-digital conversion are described. For example, a method performs an analog-to-digital conversion of an analog input to a digital output including a set of bits, the set of bits including a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit.

First claim

What is claimed is:

1. An apparatus comprising:
at least one processor; and
at least one memory including instruction code;
the at least one memory and the instruction code being configured to, with the at least one processor, cause the apparatus at least to:
perform an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit, wherein performing the analog-to-digital conversion starting at the given one of the one or more additional bits following the most significant bit comprises skipping computing of a designated number of the most significant bits of the set of bits;
detect one or more designated conditions associated with the digital output produced by the analog-to-digital conversion; and
responsive to detecting at least one of the one or more designated conditions, restart the analog-to-digital conversion of the analog input to the digital input starting at another one of the bits, the other one of the bits being more significant than the given one of the one or more additional bit.

2. The apparatus of claim 1 , wherein the given one of the one or more additional bits following the most significant bit comprises a first one of the one or more additional bits following the most significant bit, and wherein restarting the analog-to-digital conversion starting at the other one of the set of bits comprises restarting the analog-to-digital conversion starting at the most significant bit.

3. The apparatus of claim 1 , wherein detecting said at least one of the one or more designated conditions is based at least in part on values of a threshold number of consecutive ones of the one or more additional bits following the given one of the one or more additional bits.

4. The apparatus of claim 3 , wherein the threshold number is selected based at least in part on at least one of: an output probability distribution of a dot-product engine performing a binary multiplication of first and second vectors; and a tolerable error in an output of the analog-to-digital conversion.

5. The apparatus of claim 1 , wherein the given one of the one or more additional bits following the most significant bit (MSB) comprises an (MSB−k)th bit, wherein restarting the analog-to-digital conversion starting at the other one of the set of bits comprises restarting the analog-to-digital conversion starting at an (MSB−k+l)th bit, and wherein l is an integer greater than or equal to one.

6. The apparatus of claim 5 , wherein a value of k is selected based at least in part on at least one of: an output probability distribution of a dot-product engine performing a binary multiplication of first and second vectors; and a tolerable error in an output of the analog-to-digital conversion.

7. A method, comprising the step of:
performing an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit, wherein performing the analog-to-digital conversion starting at the given one of the one or more additional bits following the most significant bit comprises skipping computing of a designated number of the most significant bits of the set of bits;
detecting one or more designated conditions associated with the digital output produced by the analog-to-digital conversion; and
responsive to detecting at least one of the one or more designated conditions, restarting the analog-to-digital conversion of the analog input to the digital input starting at another one of the bits, the other one of the bits being more significant than the given one of the one or more additional bits;
wherein the method is executed by processing circuitry configured to execute instruction code.

8. The method of claim 7 , wherein the given one of the one or more additional bits following the most significant bit (MSB) comprises an (MSB−k)th bit, wherein restarting the analog-to-digital conversion starting at the other one of the set of bits comprises restarting the analog-to-digital conversion starting at an (MSB−k+l)th bit, and wherein l is an integer greater than or equal to one.

9. An article of manufacture comprising a non-transitory computer-readable storage medium having embodied therein executable instruction code that when executed by a processor causes the processor to perform the step of:
performing an analog-to-digital conversion of an analog input to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits, the analog-to-digital conversion starting at a given one of the one or more additional bits following the most significant bit, wherein performing the analog-to-digital conversion starting at the given one of the one or more additional bits following the most significant bit comprises skipping computing of a designated number of the most significant bits of the set of bits;
detecting one or more designated conditions associated with the digital output produced by the analog-to-digital conversion; and
responsive to detecting at least one of the one or more designated conditions, restarting the analog-to-digital conversion of the analog input to the digital input starting at another one of the bits, the other one of the bits being more significant than the given one of the one or more additional bits.

10. The article of claim 9 , wherein the given one of the one or more additional bits following the most significant bit (MSB) comprises an (MSB−k)th bit, wherein restarting the analog-to-digital conversion starting at the other one of the set of bits comprises restarting the analog-to-digital conversion starting at an (MSB−k+l)th bit, and wherein l is an integer greater than or equal to one.

11. A system comprising:
a dot-product summation computation unit configured to perform binary multiplication of first and second vectors;
a successive approximation register analog-to-digital converter unit configured to convert an analog output of the dot-product summation computation unit to a digital output comprising a set of bits, the set of bits comprising a most significant bit and one or more additional bits; and
controller logic operatively coupled to the successive approximation register analog-to-digital converter unit, the controller logic being configured to determine values of the set of bits of the digital output based at least in part on a comparison of an output of the dot-product summation computation unit and a sequence of weighted binary codes;
wherein the sequence of weighted binary codes starts from a given one of the one or more additional bits following the most significant bit;
to detect one or more designated conditions associated with the determined values of the set of bits of the digital output; and
responsive to detecting at least one of the one or more designated conditions, to restart determination of the values of the set of bits of the digital output with a new sequence of weighted binary codes starting from another one of the bits.

12. The system of claim 11 , wherein the given one of the one or more additional bits following the most significant bit (MSB) comprises an (MSB−k)th bit, wherein the new sequence of weighted binary codes starts from an (MSB−k+l)th bit, and wherein l is an integer greater than or equal to one.

13. The system of

Assignees

• IBM

Inventors

• Kar Monodeep
• Agrawal Ankur
• Kang Mingu
• Kim Kyu-Hyoun

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title