Electronic comparison systems

Patent metadata

Field	Value
Publication number	US-10476487-B2
Application number	US-201715801535-A
Country	US
Kind code	B2
Filing date	Nov 2, 2017
Priority date	May 27, 2014
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

First claim

What is claimed is:

1. A system, comprising:
a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element connected to one of the row electrodes and one of the column electrodes;
a writing circuit configured to store selected weights in the resistive memory elements;
a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;
a reference source configured to provide one or more reference electrical signal(s), each of the reference electrical signal(s) comprising a respective reference current or a respective reference voltage;
a plurality of domain-wall neurons;
a plurality of latches; and
a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator comprises:
a respective domain-wall neuron of the plurality of domain-wall neurons, the respective domain-wall neuron connected to the respective column electrode and to the reference source; and
a latch of the plurality of latches, the respective latch configured to compare an output of the respective domain-wall neuron with a selected threshold and store a respective bit value according to the result of the comparison,

wherein:
the reference source comprises:
a reference controller programmed to sequence through a selected number of bits, starting with a most-significant bit of the selected number of bits; and
a plurality of reference circuits, each configured to provide one of the reference electrical signal(s) to a respective one of the comparators; each reference circuit comprises:
a register configured to hold respective values for the selected number of bits; and
a signal generator that provides the respective one of the reference electrical signals in response to the values in the register; and

the reference controller is configured to successively update the bits of each of the registers in the sequence according to the stored bit value in the respective one of the comparators.

2. The system according to claim 1 , further comprising a processor configured to:
receive the respective stored bit values of the comparators;
determine updated weights using the selected weights, the test electrical signals, and the received bit values; and
cause the writing circuit to store the updated weights in the resistive memory elements.

3. The system according to claim 2 , wherein the processor is configured to determine the updated weights using a neural-network training algorithm.

4. The system according to claim 1 , wherein the resistive memory elements comprise respective memristors.

5. The system according to claim 1 , wherein the reference source comprises at least one binary-weighted transistor digital-to-analog converter (DAC) configured to provide a respective reference electrical signal of the one or more reference electrical signal(s).

6. The system according to claim 1 , wherein each signal generator comprises a binary-weighted transistor digital-to-analog converter (DAC) responsive to the values in the respective register to provide the respective one of the reference electrical signals.

7. The system according to claim 1 , further comprising a processor configured to:
receive the respective bit values in the registers;
determine updated weights using the selected weights, the test electrical signals, and the received bit values; and
cause the writing circuit to store the updated weights in the resistive memory elements.

8. The system according to claim 1 , further comprising:
a plurality of one-shots connected to respective ones of the input stages to successively receive the bits of the registers, starting with most-significant bits thereof, wherein each one-shot is configured to successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then to provide a second, different bit value; and
an enable circuit connected to the outputs of the one-shots and configured to provide the enable signal if at least one of the one-shots is providing the first bit value.

9. The system according to claim 8 , further comprising a controller configured to automatically:
receive an input vector and a plurality of test vectors;
operate the writing circuit to store values from each of the test vectors in the resistive memory elements directly connected to a respective one of the column electrodes;
operate the signal source to apply the test electrical signals corresponding to the input vector;
determine which one(s) of the test vectors satisfy a selected criterion with respect to the input vector using the outputs of the one-shots.

10. The system according to claim 9 , wherein the controller is configured to automatically determine which one of the test vectors corresponds with the highest value of the values in the registers.

11. The system according to claim 8 , wherein the enable circuit comprises:
a node selectively carrying the enable signal;
a precharge circuit configured to precharge the node to a signal level different from the enable signal; and
a modification circuit configured to provide the enable signal on the node in response to the first bit value from at least one of the one-shots.

12. The system according to claim 11 , wherein:
the precharge circuit comprises a pullup;
the discharge circuit comprises respective selective pulldowns controlled by the outputs of respective ones of the one-shots;
the enable signal corresponds to a low signal level of the node; and
the signal level different from the enable signal corresponds to a high signal level of the node.

13. The system according to claim 8 , wherein the non-preferred value is zero.

14. The system according to claim 8 , wherein the first bit value is unity and the second, different bit value is zero.

15. The system according to claim 8 , wherein:
individual ones of the one-shots comprise AND gates and first and second D flip-flops (DFFs) enabled by the enable signal;
the output of the first DFF and the input of the first DFF are connected as the inputs of the AND gate; and
the output of the AND gate is connected to the input of the second DFF.

16. The system according to claim 15 , further comprising a gate circuit configured:
determine that the output of the second DFF is the second, different bit value and the enable signal is provided; and
in response, set the input of the first DFF to the non-preferred value.

17. A system, comprising:
a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element connected to one of the row electrodes and one of the column electrodes;
a writing circuit configured to store selected weights in the resistive memory elements;
a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;
a reference source configured to provide one or more reference electrical signal(s);
a plurality of domain-wall neurons;
a plurality of latches; and
a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator includes:
a respective domain-wall neuron of the plurality of domain-wall neurons, the respective domain-wall neuron connected to th

Assignees

• Purdue Research Foundation

Inventors

• Roy Kaushik
• Sharad Mrigank

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/54 Primary

  using elements simulating biological cells, e.g. neuron · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title