Sigma-delta analogue to digital converter

US12418302B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12418302-B2
Application numberUS-202318455291-A
CountryUS
Kind codeB2
Filing dateAug 24, 2023
Priority dateSep 2, 2022
Publication dateSep 16, 2025
Grant dateSep 16, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source.

First claim

Opening claim text (preview).

The invention claimed is: 1. A sigma-delta ADC comprising: a first-input-terminal configured to receive a first-analogue-input-signal; a second-input-terminal configured to receive a second-analogue-input-signal; a third-input-terminal configured to receive a third-analogue-input-signal; a reference-terminal; a first-amplifier-stage comprising: a first-amplifier-first-input-terminal; a first-amplifier-second-input-terminal; a first-input-resistor connected in series between the first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between the second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between the third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and the first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and the first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selection-switch connected in series between the first-feedback-node and the first terminal of the first-feedback-current-source; a second-feedback-selection-switch connected in series between the second-feedback-node and the first terminal of the second-feedback-current-source; and a third-feedback-selection-switch connected in series between the third-feedback-node and the first terminal of the first-feedback-current-source. 2. The sigma-delta ADC of claim 1 , further including one or more: even-input-terminals each configured to receive a respective even-analogue-input-signal; even-input-resistors, each connected in series between a respective one of the even-input-terminals and a respective even-feedback-node; even-multiplexer-switches, each connected in series between a respective one of the even-feedback-nodes and the first-amplifier-second-input-terminal; and even-feedback-selection-switches, each connected in series between a respective one of the even-feedback-nodes and the first terminal of the first-feedback-current-source. 3. The sigma-delta ADC of claim 2 , further including one or more: odd-input-terminals each configured to receive a respective odd-analogue-input-signal; odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node; odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source. 4. The sigma-delta ADC of claim 1 , further including one or more: odd-input-terminals each configured to receive a respective odd-analogue-input-signal; odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node; odd-multiplexer-switches, each connected in series between a respective one of the odd-feedback-nodes and the first-amplifier-first-input-terminal; and odd-feedback-selection-switches, each connected in series between a respective one of the odd-feedback-nodes and the first terminal of the second-feedback-current-source. 5. The sigma-delta ADC of claim 1 , wherein: the first-multiplexer-switch is connected in series between the first-feedback-node and an even-amplifier-connection-node; the second-multiplexer-switch is connected in series between the second-feedback-node and an odd-amplifier-connection-node; a third-multiplexer-switch connected in series between the third-feedback-node and the even-amplifier-connection-node; the sigma-delta ADC further comprising: a first-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-second-input-terminal; a second-even-amplifier-connection-switch connected in series between the even-amplifier-connection-node and the first-amplifier-first-input-terminal; a first-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-first-input-terminal; and a second-odd-amplifier-connection-switch connected in series between the odd-amplifier-connection-node and the first-amplifier-second-input-terminal. 6. The sigma-delta ADC of claim 5 , wherein: the first-feedback-selection-switch is connected in series between the first-feedback-node and an even-current-source-connection-node; the second-feedback-selection-switch is connected in series between the second-feedback-node and an odd-current-source-connection-node; a third-feedback-selection-switch connected in series between the third-feedback-node and the even-current-source-connection-node; the sigma-delta ADC further comprising: a first-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the first-feedback-current-source; a second-even-current-source-connection-switch connected in series between the even-current-source-connection-node and the second-feedback-current-source; a first-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the second-feedback-current-source; and a second-odd-current-source-connection-switch connected in series between the odd-current-source-connection-node and the first-feedback-current-source. 7. The sigma-delta ADC of claim 6 , further comprising: a first-feedback-switch connected in series between: i) the first-feedback-current-source; and ii) each of the first-even-current-source-connection-switch and the second-odd-current-source-connection-switch, such that the first-feedback-switch can selectively disconnect the first-feedback-current-source from the even-current-source-connection-node and the odd-current-source-connection-node; and a second-feedback-switch connected in series between: i) the second-feedback-current-source; and ii) each of the second-even-current-source-connection-switch and the first-odd-current-source-connection-switch, such that the second-feedback-switch can selectively disconnect the second-feedback-current-source from the even-current-source-connection-node and the odd-current-source-connection-node. 8. The sigma-delta ADC of claim 5 , further including one or more: even-input-terminals each configured to receive a respective even-analogue-input-signal; even-input-resistors, each connected in series between a respective one of the even-input-terminals and a respective even-feedback-node; even-multiplexer-switches, each connected in series between a respective one of the even-feedback-nodes and the first-amplifier-second-input-terminal; and even-feedback-selection-switches, each connected in series between a respective one of the even-feedback-nodes and the first terminal of the first-feedback-current-source. 9. The sigma-delta ADC of claim 5 , further including one or more: odd-input-terminals each configured to receive a respective odd-analogue-input-signal; odd-input-resistors, each connected in series between a respective one of the odd-input-terminals and a respective odd-feedback-node; odd-multiplexer-switches, each connected in series between a respect

Assignees

Inventors

Classifications

  • H03M3/458Primary

    Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

  • the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter · CPC title

  • Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators (of digital delta-sigma modulators H03M7/3004) · CPC title

  • Details of the digital/analogue conversion in the feedback path · CPC title

  • H03M1/123Primary

    Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters · CPC title

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What does patent US12418302B2 cover?
A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the fi…
Who is the assignee on this patent?
Nxp Usa Inc
What technology area does this patent fall under?
Primary CPC classification H03M3/458. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 16 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).